공통 모드 아티팩트 제거 루프가 있는 저전력 재구성 가능한 뇌 신경 인터페이스 아날로그 프론트엔드 집적회로

Translated title of the contribution: A Low-power Reconfigurable Neural Interface Analog Front-end IC with Common-mode Artifact Cancellation Loop

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a low-power and low-noise analog front-end (AFE) for conditioning of neural signals. The proposed AFE consists of a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), and also includes a common-mode cancellation loop (CMCL) circuit that can withstand large common-mode artifacts generated from the stimulator part of the neural interface. The CMCL circuit is controlled by comparators and logic gates to operate only when a large common-mode input is received. The proposed PGA is capable of additional gain adjustments of 1, 2, 5, and 10 times to amplify very small neural signals. In addition, the PGA is designed to have constant bandwidth regardless of additional gain adjustment. Since neural signals have different frequency bands, the proposed circuit is designed to enable recording by discriminating between action potential (AP) and local field potential (LFP) signals by controlling the bandwidth using a narrow band buffer. The high-pass cutoff frequency is adjustable between sub-1㎐ and 500 ㎐, and the low-pass cutoff frequency is adjustable from 290 ㎐ to 12 ㎑. The voltage gain of the entire proposed AFE is 40 ㏈-60 ㏈, and the input referred noise (IRN) of 1.92 ㎶rms is achieved when CMCL is not operating in the 1-12 ㎑ band, while the IRN is 3.2 ㎶rms when CMCL is enabled. The total power consumption of the proposed AFE is 2.6 ㎼, and it is designed using a 0.18-㎛ CMOS process.
Translated title of the contributionA Low-power Reconfigurable Neural Interface Analog Front-end IC with Common-mode Artifact Cancellation Loop
Original languageKorean
Pages (from-to)28-34
Number of pages7
Journal전자공학회논문지
Volume60
Issue number6
DOIs
StatePublished - 2023

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