Abstract
We have simulated the process induced warpage for panel level package using finite element method. Silicon chips of 5 × 5 mm2 were redistributed on 122.4 × 93.6 mm2 size panel and the total number of redistributed chips was 221. The warpage at each process step, for example, ① EMC molding, ② attachment of detach core, ③ heating, ④ removal of a carrier, and ⑤ cooling was simulated using ANSYS and the effects of detach core and carrier materials on the warpage were investigated. The warpage behaved complexly depending on the materials for the detach core and carrier.
However, glass carrier showed the lower warpage than FR4 carrier regardless of detach core material, and the minimum warpage was observed when the glass was used for the detach core and carrier at the same time.
However, glass carrier showed the lower warpage than FR4 carrier regardless of detach core material, and the minimum warpage was observed when the glass was used for the detach core and carrier at the same time.
| Translated title of the contribution | Process Induced Warpage Simulation for Panel Level Package |
|---|---|
| Original language | Korean |
| Pages (from-to) | 41-45 |
| Number of pages | 5 |
| Journal | 마이크로전자 및 패키징학회지 |
| Volume | 25 |
| Issue number | 4 |
| State | Published - Dec 2018 |