병렬 CRC 생성 방식을 활용한 BCH 코드 복호기 설계

This paper introduces a BCH code decoder using parallel cyclic redundancy check (CRC) generation. Using a conventional parallel syndrome generator with a linear feedback shift register (LFSR), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in 0.35-μm CMOS process.