Abstract
Recently, intensive research has been performed for reducing video decoder energy consumption, especially based on DVFS (Dynamic Voltage and Frequency Scaling) technique. Our previous work [1] has proposed the optimal DVFS algorithm for energy reduction in video decoders. In spite of the mathematical optimality of the algorithm, the precondition of known frame decoding cycle/complexity limits its application to some realistic scenarios. This paper overcomes this limitation by frame data size-based estimation of frame decoding complexity. The proposed decoding complexity estimation method shows over 90% accuracy. And with this estimation method and buffer underflow margin of around 20% of frame size, almost same power consumption reduction performance as the optimal algorithm can be achieved.
Translated title of the contribution | Power-Minimizing DVFS Algorithm Using Estimation of Video Frame Decoding Complexity |
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Original language | Korean |
Pages (from-to) | 46-53 |
Number of pages | 8 |
Journal | 한국통신학회논문지B |
Volume | 38 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2013 |