웨이퍼 레벨 적층 공정에서 웨이퍼 휘어짐이 정렬 오차에 미치는 영향

Translated title of the contribution: Effects of Wafer Warpage on the Misalignment in Wafer Level Stacking Process

Research output: Contribution to journalArticlepeer-review

Abstract

In this study, the effects of wafer warpage on the misalignment during wafer stacking process were investigated. The wafer with $45{\mu}m$ bow height warpage was purposely fabricated by depositing Cu thin film on a silicon wafer and the bonding misalignment after bonding was observed to range from $6{\mu}m$ to $15{\mu}m$. This misalignment could be explained by a combination of $5{\mu}m$ radial expansion and $10{\mu}m$ linear slip. The wafer warpage seemed to be responsible for the slip-induced misalignment instead of radial expansion misalignment.
Translated title of the contributionEffects of Wafer Warpage on the Misalignment in Wafer Level Stacking Process
Original languageKorean
Pages (from-to)71-74
Number of pages4
Journal마이크로전자 및 패키징학회지
Volume20
Issue number3
DOIs
StatePublished - Sep 2013

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