Abstract
Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.
| Translated title of the contribution | Cu/SiO2 CMP Process for Wafer Level Cu Bonding |
|---|---|
| Original language | Korean |
| Pages (from-to) | 47-51 |
| Number of pages | 5 |
| Journal | 마이크로전자 및 패키징학회지 |
| Volume | 20 |
| Issue number | 2 |
| DOIs | |
| State | Published - Jun 2013 |