Abstract
In this paper, a dual-channel CMOS analog front-end IC for neural recording applications is designed. The proposed low-power low-noise IC is composed of a neural amplifier for processing neural signals that can be observed in the frequency range of 1 Hz to several kHz, a variable gain amplifier for controlling additional gain and bandwidth, control circuit that can reduce power consumption of the overall analog front-end and adjust the re-set time of each channel. A complementary cascode input based operational transconductance amplifier(OTA) is designed for the low-power neural amplifier, while the variable gain amplifier uses a current-mirror-based OTA with a focus on low power, and the control circuit applies basic digital logic circuits. The variable gain amplifier has the voltage gain with a range of 6 dB to 24 dB and can adjust high-pass cutoff frequency from 1 Hz to 440 Hz and low-pass cutoff frequency from 600 Hz to 10 kHz. The control circuit selects a channel according to the control signal, controls the initial re-set time, and cutoffs the power to the unselected channel. The overall analog front-end IC has a maximum voltage gain of 63.7 dB and a noise efficiency factor of 1.96 with an integrated input referred noise of 3.49 μVrms for the 1 Hz to 10 kHz band. It consumes 2 μW of power from the 1-V power supply while the chip layout area per channel is 0.13 mm² and is designed using 0.18-μm standard CMOS process.
| Translated title of the contribution | An Ultra Low-Power Low-Noise Dual-Channel CMOS Neural Recording Analog IC |
|---|---|
| Original language | Korean |
| Pages (from-to) | 21-28 |
| Number of pages | 8 |
| Journal | 전자공학회논문지 |
| Volume | 55 |
| Issue number | 3 |
| DOIs | |
| State | Published - 2018 |