초저전력 ECoG 신호 기록 아날로그 프론트-엔드 집적회로

In this paper, an implantable analog front-end integrated circuit (AFE IC) for electrocorticography (ECoG) recording incorporating a low-noise neural amplifier (LNA) and successive approximation register analog-to-digital converter (SAR ADC) is presented. The AC-coupled capacitive-feedback LNA is designed using an ultra low-power operational transconductance amplifier (OTA) with inverter-stacking, gain-boosting, and floating body techniques. The LNA operates at 1-V supply and achieves 1.27 of noise efficiency factor with 40 dB of voltage gain, 520 Hz bandwidth, 6.04 μVrms of integrated input referred noise and 15.5 nW power consumption. The designed SAR ADC uses a VCM-based monotonic capacitor switching scheme saving 97.66 % of switching power while consuming a quarter of CDAC area compared to conventional SAR ADC. The proposed EVEN/ODD technique using new dynamic logic block architecture reduces the complexity of the digital blocks and minimizes the digital power consumption and logic delay. In addition, asynchronous clock and non-binary weight redundant capacitor techniques are used to improve the ADC power efficiency and linearity. The designed SAR ADC achieves 61.87 dB SNDR, 78.78 dB SFDR, 9.985 bit ENOB, FoM of 0.825 fJ/conversion-step while consuming 83.6 nW power consumption at 0.5-V supply voltage and 100 kS/s sampling rate. The ECoG recording AFE IC designed using 65-nm CMOS process and occupies 0.083 mm² of chip area.