0.35-μm CMOS-process-based voltage-to-current converter design for an analog OFDM device

For a low-power wireless communication, a fast-Fourier-transform (FFT) LSI for an orthogonal frequency division multiplexing (OFDM) system has been implemented with current-mode circuits. In this current-mode OFDM system, a voltage-current converter (VIC) should be designed with an operating frequency of more than 40 MHz, because the frequency bandwidth of the OFDM signal is recommended as 20 MHz in IEEE 802.11a. Moreover, the VIC should be designed with a small chip size, and a low-power consumption, assuming that the FFT LSI and a VIC are combined with a single chip. In this paper, the VIC was designed with the active chip size of 115 μm × 29.3 μm and implemented with a 0.35-μm CMOS process. The implemented IVC was measured to have a negligibly small dc current offset at an operating frequency of 120 MHz, and the power consumption was 1.32 mW at Vdd = 3.3 V.