3-D integration using wafer bonding

Use of wafer bonding technology is a promising approach to 3-D integration, which aims to alleviate furore Cu/low-k interconnect bottlenecks and enables multifunctional system integration. This paper describes a specific approach, incorporating wafer alignment and wafer bonding of two 200 mm silicon wafers, along with subsequent processing steps. Our approach using dielectrics as the bonding glue layer involves three critical processing steps: wafer alignment and bonding, wafer thinning, and high-aspect-ratio via vertical interconnection using damascene patterning. A passive test structure has been designed to demonstrate the feasibility of this technology. Our results to date are quite promising, although additional research and development is needed to fully evaluate the technological viability of this 3-D approach.