TY - GEN
T1 - 4.1 A 16GHz, 41kHz rms Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
AU - Renukaswamy, Pratap Tumkur
AU - Vaesen, Kristof
AU - Markulic, Nereo
AU - Derudder, Veerle
AU - Park, Dae Woong
AU - Wambacq, Piet
AU - Craninckx, Jan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - FMCW radars are the key components for contactless range and motion sensing in industrial and healthcare applications. The radar-sensor performance, such as chirp bandwidth (textBWctexthitextrp), chirp slope, and frequency-modulation (FM) linearity, are determined by the FMCW chirp generator. When battery powered, the radar should be able to operate in a duty-cycled mode with minimal overhead, i.e., fast startup, fast lock at the start of every chirp burst, and minimal reset time in-between chirps, without degrading the radar range and Doppler performance. This work presents a robust fast-lock-acquisition charge-pump (CP)-PLL with a PFO for duty-cycled chirp generation. A fractional-N CP-PLL in a two-point-modulation (TPM) architecture breaks the trade-off between the PLL bandwidth and fast-chirp synthesis [1], [2]. A time-domain sign-extraction by using a 1 b TOC [3] enables the background calibration. A phase-offset-compensating digital-to-time converter (POC-OTC) assists the sign-extraction by compensating the positive/negative phase offsets generated within the type-Il PLL loop.
AB - FMCW radars are the key components for contactless range and motion sensing in industrial and healthcare applications. The radar-sensor performance, such as chirp bandwidth (textBWctexthitextrp), chirp slope, and frequency-modulation (FM) linearity, are determined by the FMCW chirp generator. When battery powered, the radar should be able to operate in a duty-cycled mode with minimal overhead, i.e., fast startup, fast lock at the start of every chirp burst, and minimal reset time in-between chirps, without degrading the radar range and Doppler performance. This work presents a robust fast-lock-acquisition charge-pump (CP)-PLL with a PFO for duty-cycled chirp generation. A fractional-N CP-PLL in a two-point-modulation (TPM) architecture breaks the trade-off between the PLL bandwidth and fast-chirp synthesis [1], [2]. A time-domain sign-extraction by using a 1 b TOC [3] enables the background calibration. A phase-offset-compensating digital-to-time converter (POC-OTC) assists the sign-extraction by compensating the positive/negative phase offsets generated within the type-Il PLL loop.
UR - http://www.scopus.com/inward/record.url?scp=85151718946&partnerID=8YFLogxK
U2 - 10.1109/ISSCC42615.2023.10067404
DO - 10.1109/ISSCC42615.2023.10067404
M3 - Conference contribution
AN - SCOPUS:85151718946
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 74
EP - 76
BT - 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE International Solid-State Circuits Conference, ISSCC 2023
Y2 - 19 February 2023 through 23 February 2023
ER -