A 0.25 pJ/bit Data-Rate-Dependent Reconfigurable Receiver With Dual-Mode Divider for Low-Power DDR Memory Interfaces

This paper presents a data-rate-dependent reconfigurable receiver for low-power DDR (LPDDR) memory interfaces covering data rates of 0.8-to-9 Gb/s. The receiver comprises a clock buffer, a quadrature clock corrector (QCC), a reconfigurable decision feedback equalizer (RDFE), a dual mode divider, and a bidirectional transition controller (BTC). The proposed reconfigurable receiver can select the sampling mode according to the speed of the input DQ. At high speeds, intersymbol interference removal can be done through equalization mode, which performs DFE using quadrature clocks. However, at low speeds, power consumption can be optimized via amplification mode, which simply amplifies input DQ using a half-rate clock with DFE turned off. The test chip was fabricated in a 28 nm CMOS process. The measurement results of the chip show an energy efficiency improvement to the DFE at 800 Mb/s by approximately 55%. Hence, energy efficiency improved from 2.13 pJ/b to 0.96 pJ/b for the proposed method.