A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison

Sang Hoon Lee; Won Young Lee

doi:10.1109/ISOCC53507.2021.9613979

A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a low noise 0.6-V 400-KS/s asynchronous successive approximation register (SAR) analog-To-digital converter (ADC) with time domain comparator. The VCDL-based time domain comparator suppresses noise at low voltages but requires significant conversion time. Therefore, the sampling rate of the low voltage SAR ADC is increased by using a double-Tail comparator and asynchronous logic. An implemented 10-bit ADC in a 180-nm CMOS technology occupies 1130μm x 740μm. At a 0.6-V supply voltage and a 400-KS/s sampling rate, the proposed SAR ADC achieves a signal-To-noise and distortion ratio (SNDR) of 56.59 and an effective number of bits (ENOB) of 9.13 bits.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	87-88
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613979
State	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 6 Oct 2021 → 9 Oct 2021

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	6/10/21 → 9/10/21

Keywords

analog-To-digital converter
asynchronous
double-Tail comparator
voltage-controlled delay line (VCDL)

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10.1109/ISOCC53507.2021.9613979

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@inproceedings{3e0870ec9a24477f8c85cc2c3f6efdec,

title = "A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison",

abstract = "This paper presents a low noise 0.6-V 400-KS/s asynchronous successive approximation register (SAR) analog-To-digital converter (ADC) with time domain comparator. The VCDL-based time domain comparator suppresses noise at low voltages but requires significant conversion time. Therefore, the sampling rate of the low voltage SAR ADC is increased by using a double-Tail comparator and asynchronous logic. An implemented 10-bit ADC in a 180-nm CMOS technology occupies 1130μm x 740μm. At a 0.6-V supply voltage and a 400-KS/s sampling rate, the proposed SAR ADC achieves a signal-To-noise and distortion ratio (SNDR) of 56.59 and an effective number of bits (ENOB) of 9.13 bits.",

keywords = "analog-To-digital converter, asynchronous, double-Tail comparator, voltage-controlled delay line (VCDL)",

author = "Lee, \{Sang Hoon\} and Lee, \{Won Young\}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613979",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "87--88",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

}

Lee, SH & Lee, WY 2021, A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 87-88, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 6/10/21. https://doi.org/10.1109/ISOCC53507.2021.9613979

A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison. / Lee, Sang Hoon ; Lee, Won Young.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 87-88 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison

AU - Lee, Sang Hoon

AU - Lee, Won Young

PY - 2021

Y1 - 2021

N2 - This paper presents a low noise 0.6-V 400-KS/s asynchronous successive approximation register (SAR) analog-To-digital converter (ADC) with time domain comparator. The VCDL-based time domain comparator suppresses noise at low voltages but requires significant conversion time. Therefore, the sampling rate of the low voltage SAR ADC is increased by using a double-Tail comparator and asynchronous logic. An implemented 10-bit ADC in a 180-nm CMOS technology occupies 1130μm x 740μm. At a 0.6-V supply voltage and a 400-KS/s sampling rate, the proposed SAR ADC achieves a signal-To-noise and distortion ratio (SNDR) of 56.59 and an effective number of bits (ENOB) of 9.13 bits.

AB - This paper presents a low noise 0.6-V 400-KS/s asynchronous successive approximation register (SAR) analog-To-digital converter (ADC) with time domain comparator. The VCDL-based time domain comparator suppresses noise at low voltages but requires significant conversion time. Therefore, the sampling rate of the low voltage SAR ADC is increased by using a double-Tail comparator and asynchronous logic. An implemented 10-bit ADC in a 180-nm CMOS technology occupies 1130μm x 740μm. At a 0.6-V supply voltage and a 400-KS/s sampling rate, the proposed SAR ADC achieves a signal-To-noise and distortion ratio (SNDR) of 56.59 and an effective number of bits (ENOB) of 9.13 bits.

KW - analog-To-digital converter

KW - asynchronous

KW - double-Tail comparator

KW - voltage-controlled delay line (VCDL)

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U2 - 10.1109/ISOCC53507.2021.9613979

DO - 10.1109/ISOCC53507.2021.9613979

M3 - Conference contribution

AN - SCOPUS:85123381221

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 87

EP - 88

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparison

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Keywords

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