@inproceedings{5b27add98e8d4e6a96c4933f044f471c,
title = "A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS",
abstract = "This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful layout are adopted to obtain high-resolution in a low-supply. The ADC features 12-bit resolution, 100-MS/s sampling rate, differential nonlinearity (DNL) of ±0.58 LSB, integral nonlinearity (INL) of ±2.79 LSB, and power consumption of 30.4 mW. With a sampling frequency of a 100-MS/s and an input of a 2.4 MHz, the ADC achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 59.02 dB and 63.22 dB, at a supply voltage of 1.1 V, respectively.",
keywords = "ADC, CMOS, Pipelined",
author = "Nam, \{Jae Won\} and Jeon, \{Young Deuk\} and Yun, \{Seok Ju\} and Roh, \{Tae Moon\} and Kwon, \{Jong Kee\}",
year = "2011",
doi = "10.1109/isocc.2011.6138617",
language = "English",
isbn = "9781457707100",
series = "2011 International SoC Design Conference, ISOCC 2011",
publisher = "IEEE Computer Society",
pages = "405--407",
booktitle = "2011 International SoC Design Conference, ISOCC 2011",
note = "8th International SoC Design Conference 2011, ISOCC 2011 ; Conference date: 17-11-2011 Through 18-11-2011",
}