A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS

Jae Won Nam; Mohsen Hassanpourghadi; Aoyang Zhang; Mike Shuo Wei Chen

doi:10.1109/VLSIC.2016.7573516

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS

Jae Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo Wei Chen

Electronic Engineering Program

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509006342
DOIs	https://doi.org/10.1109/VLSIC.2016.7573516
State	Published - 21 Sep 2016
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 14 Jun 2016 → 17 Jun 2016

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2016-September

Conference

Conference	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	14/06/16 → 17/06/16

Keywords

ADC
CMOS
SAR
high speed
time interleave

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10.1109/VLSIC.2016.7573516

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Nam, J. W., Hassanpourghadi, M., Zhang, A., & Chen, M. S. W. (2016). A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. In 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 Article 7573516 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2016.7573516

Nam, Jae Won ; Hassanpourghadi, Mohsen ; Zhang, Aoyang et al. / A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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title = "A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS",

abstract = "A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.",

keywords = "ADC, CMOS, SAR, high speed, time interleave",

author = "Nam, \{Jae Won\} and Mohsen Hassanpourghadi and Aoyang Zhang and Chen, \{Mike Shuo Wei\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",

year = "2016",

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doi = "10.1109/VLSIC.2016.7573516",

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Nam, JW, Hassanpourghadi, M, Zhang, A & Chen, MSW 2016, A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. in 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016., 7573516, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2016-September, Institute of Electrical and Electronics Engineers Inc., 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 14/06/16. https://doi.org/10.1109/VLSIC.2016.7573516

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. / Nam, Jae Won; Hassanpourghadi, Mohsen; Zhang, Aoyang et al.
2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7573516 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.

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Nam JW, Hassanpourghadi M, Zhang A, Chen MSW. A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. In 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7573516. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2016.7573516

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS

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