TY - JOUR
T1 - A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency
AU - Kim, Keun Mok
AU - Choi, Kyung Sik
AU - Jung, Hyunki
AU - Yun, Byeonghun
AU - Xu, Jinglong
AU - Ko, Jinho
AU - Lee, Sang Gug
N1 - Publisher Copyright:
© 1966-2012 IEEE.
PY - 2023/6/1
Y1 - 2023/6/1
N2 - This article presents an interference-resilient high-sensitivity binary frequency-shift keying (BFSK) multi-channel wake-up receiver (WuRX) supporting 900-MHz bands for low-power wide-area network (LPWAN) applications. The proposed WuRX uses a direct-conversion architecture, a frequency-to-energy demodulator, and a 4096-bit correlator. Direct conversion using a 50%-to-25% duty-cycle conversion mixer and two-stage ring voltage-controlled oscillator (VCO) minimizes the power consumption. The frequency-to-energy demodulator offers a process-voltage-temperature (PVT) variation-tolerant symbol recovery based on an image rejection n -path filter (IRNF), a poly-phase filter (PPF), and a quadrature envelope detector (ED). The 4096-bit correlator provides a digital processing gain of about 17 dB, improving both the sensitivity and the selectivity. To reduce the power consumption further, the proposed WuRX supports an asynchronous duty-cycling operation based on repetition of the wake-up code. Implemented in the 55-nm complementary metal-oxide-semiconductor (CMOS), the proposed WuRX achieves sensitivity of -124 dBm in the always-on mode while dissipating 781 μ W. For the duty-cycling mode with wake-up codes repeated 15 times, the proposed WuRX exhibits the same sensitivity of -124 dBm with reduced power consumption of 114 μ W and extended wake-up latency of 1.966 s. The proposed WuRX shows robust interference resilience with a signal-to-interference ratio (SIR) of -76 dB at a 20-MHz offset against a continuous wave (CW). The CMOS radio module, including the proposed WuRX, showed packet-error rates (PERs) of 0% and 5.7% in the 4.8- and 9.8-km ground-to-ground wireless communication tests, respectively.
AB - This article presents an interference-resilient high-sensitivity binary frequency-shift keying (BFSK) multi-channel wake-up receiver (WuRX) supporting 900-MHz bands for low-power wide-area network (LPWAN) applications. The proposed WuRX uses a direct-conversion architecture, a frequency-to-energy demodulator, and a 4096-bit correlator. Direct conversion using a 50%-to-25% duty-cycle conversion mixer and two-stage ring voltage-controlled oscillator (VCO) minimizes the power consumption. The frequency-to-energy demodulator offers a process-voltage-temperature (PVT) variation-tolerant symbol recovery based on an image rejection n -path filter (IRNF), a poly-phase filter (PPF), and a quadrature envelope detector (ED). The 4096-bit correlator provides a digital processing gain of about 17 dB, improving both the sensitivity and the selectivity. To reduce the power consumption further, the proposed WuRX supports an asynchronous duty-cycling operation based on repetition of the wake-up code. Implemented in the 55-nm complementary metal-oxide-semiconductor (CMOS), the proposed WuRX achieves sensitivity of -124 dBm in the always-on mode while dissipating 781 μ W. For the duty-cycling mode with wake-up codes repeated 15 times, the proposed WuRX exhibits the same sensitivity of -124 dBm with reduced power consumption of 114 μ W and extended wake-up latency of 1.966 s. The proposed WuRX shows robust interference resilience with a signal-to-interference ratio (SIR) of -76 dB at a 20-MHz offset against a continuous wave (CW). The CMOS radio module, including the proposed WuRX, showed packet-error rates (PERs) of 0% and 5.7% in the 4.8- and 9.8-km ground-to-ground wireless communication tests, respectively.
KW - Binary frequency-shift keying (BFSK)
KW - Internet-of-Things (IoT)
KW - duty cycle
KW - low-power wide-area network (LPWAN)
KW - massive machine-type communications (mMTC)
KW - receiver (RX)
KW - ultra-low-power (ULP)
KW - wake-up RX (WuRX)
UR - http://www.scopus.com/inward/record.url?scp=85140728397&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2022.3208563
DO - 10.1109/JSSC.2022.3208563
M3 - Article
AN - SCOPUS:85140728397
SN - 0018-9200
VL - 58
SP - 1667
EP - 1680
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -