A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS

Jae Won Nam, Mike Shuo Wei Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

An ADC-based receiver is demonstrated for NRZ/PAM4 modulation, featuring a TDC-assisted multi-bit/cycle asynchronous SAR ADC with embedded IIR equalization filter. It re-uses the existing sampling network of time-interleaved ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65 nm CMOS and achieves an efficiency of 2.43 pJ/b using 12.8-Gbuad PAM4. The 8-way time-interleaved ADC measures 4.84 peak effective-number-of-bit with power consumption of 36.3 mW.

Original languageEnglish
Title of host publication2019 IEEE Custom Integrated Circuits Conference, CICC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538693957
DOIs
StatePublished - Apr 2019
Event40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States
Duration: 14 Apr 201917 Apr 2019

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2019-April
ISSN (Print)0886-5930

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
Country/TerritoryUnited States
CityAustin
Period14/04/1917/04/19

Keywords

  • CMOS
  • component; ADC-base receiver
  • equalization
  • IIR
  • PAM4
  • SAR
  • wireline

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