A 12.8-Gbaud ADC-Based Wireline Receiver with Embedded IIR Equalizer

Jae Won Nam; Mike Shuo Wei Chen

doi:10.1109/JSSC.2019.2956395

A 12.8-Gbaud ADC-Based Wireline Receiver with Embedded IIR Equalizer

Jae Won Nam, Mike Shuo Wei Chen

Electronic Engineering Program

University of Southern California

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active G_m-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal-oxide-semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm² core area.

Original language	English
Article number	8928495
Pages (from-to)	557-566
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	55
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2019.2956395
State	Published - Mar 2020

Keywords

Complementary metal-oxide-semiconductor (CMOS)
equalization
successive approximation register analog-to-digital converter (SAR ADC)
switched-capacitor filter
wireline

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10.1109/JSSC.2019.2956395

Cite this

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title = "A 12.8-Gbaud ADC-Based Wireline Receiver with Embedded IIR Equalizer",

abstract = "This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal-oxide-semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm2 core area.",

keywords = "Complementary metal-oxide-semiconductor (CMOS), equalization, successive approximation register analog-to-digital converter (SAR ADC), switched-capacitor filter, wireline",

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doi = "10.1109/JSSC.2019.2956395",

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N2 - This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal-oxide-semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm2 core area.

AB - This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal-oxide-semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm2 core area.

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KW - switched-capacitor filter

KW - wireline

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ER -

A 12.8-Gbaud ADC-Based Wireline Receiver with Embedded IIR Equalizer

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Keywords

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