A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort

This brief presents a continuous-rate digital clock and data recovery (CDR). The proposed frequency detector comprises coarse and fine detection to enable frequency acquisition and robust harmonic lock prevention. Step-function pulses in the coarse stage enable rapid steady-state convergence and enhance resistance to harmonic locking, while the fine stage performs precise frequency adjustment. The proposed CDR was fabricated in a 28-nm technology and the active area is 0.12 mm2. The proposed mechanism significantly improves acquisition speed, achieving a lock time of 1.49μ s at a 170% frequency offset. At 8.1 Gbps with a 1-V supply, it consumes 18.15 mW, corresponding to an energy efficiency of 2.24 pJ/b.