A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort

Hyun Bin Lee; Won Young Lee

doi:10.1109/TCSII.2025.3582913

A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort

Hyun Bin Lee, Won Young Lee

Media IT Engineering Program

Research output: Contribution to journal › Article › peer-review

Abstract

This brief presents a continuous-rate digital clock and data recovery (CDR). The proposed frequency detector comprises coarse and fine detection to enable frequency acquisition and robust harmonic lock prevention. Step-function pulses in the coarse stage enable rapid steady-state convergence and enhance resistance to harmonic locking, while the fine stage performs precise frequency adjustment. The proposed CDR was fabricated in a 28-nm technology and the active area is 0.12 mm². The proposed mechanism significantly improves acquisition speed, achieving a lock time of 1.49 μs at a 170% frequency offset. At 8.1 Gbps with a 1-V supply, it consumes 18.15 mW, corresponding to an energy efficiency of 2.24 pJ/b.

Original language	English
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
DOIs	https://doi.org/10.1109/TCSII.2025.3582913
State	Accepted/In press - 2025

Keywords

anti-harmonic lock
Clock and data recovery
fast frequency acquisition
referenceless
wide range

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2025.3582913

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title = "A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort",

abstract = "This brief presents a continuous-rate digital clock and data recovery (CDR). The proposed frequency detector comprises coarse and fine detection to enable frequency acquisition and robust harmonic lock prevention. Step-function pulses in the coarse stage enable rapid steady-state convergence and enhance resistance to harmonic locking, while the fine stage performs precise frequency adjustment. The proposed CDR was fabricated in a 28-nm technology and the active area is 0.12 mm2. The proposed mechanism significantly improves acquisition speed, achieving a lock time of 1.49 μs at a 170\% frequency offset. At 8.1 Gbps with a 1-V supply, it consumes 18.15 mW, corresponding to an energy efficiency of 2.24 pJ/b.",

keywords = "anti-harmonic lock, Clock and data recovery, fast frequency acquisition, referenceless, wide range",

author = "Lee, \{Hyun Bin\} and Lee, \{Won Young\}",

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year = "2025",

doi = "10.1109/TCSII.2025.3582913",

language = "English",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

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AU - Lee, Hyun Bin

AU - Lee, Won Young

PY - 2025

Y1 - 2025

N2 - This brief presents a continuous-rate digital clock and data recovery (CDR). The proposed frequency detector comprises coarse and fine detection to enable frequency acquisition and robust harmonic lock prevention. Step-function pulses in the coarse stage enable rapid steady-state convergence and enhance resistance to harmonic locking, while the fine stage performs precise frequency adjustment. The proposed CDR was fabricated in a 28-nm technology and the active area is 0.12 mm2. The proposed mechanism significantly improves acquisition speed, achieving a lock time of 1.49 μs at a 170% frequency offset. At 8.1 Gbps with a 1-V supply, it consumes 18.15 mW, corresponding to an energy efficiency of 2.24 pJ/b.

AB - This brief presents a continuous-rate digital clock and data recovery (CDR). The proposed frequency detector comprises coarse and fine detection to enable frequency acquisition and robust harmonic lock prevention. Step-function pulses in the coarse stage enable rapid steady-state convergence and enhance resistance to harmonic locking, while the fine stage performs precise frequency adjustment. The proposed CDR was fabricated in a 28-nm technology and the active area is 0.12 mm2. The proposed mechanism significantly improves acquisition speed, achieving a lock time of 1.49 μs at a 170% frequency offset. At 8.1 Gbps with a 1-V supply, it consumes 18.15 mW, corresponding to an energy efficiency of 2.24 pJ/b.

KW - anti-harmonic lock

KW - Clock and data recovery

KW - fast frequency acquisition

KW - referenceless

KW - wide range

UR - https://www.scopus.com/pages/publications/105009379845

U2 - 10.1109/TCSII.2025.3582913

DO - 10.1109/TCSII.2025.3582913

M3 - Article

AN - SCOPUS:105009379845

SN - 1549-7747

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

ER -

A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort

Abstract

Keywords

UN SDGs

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