A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core

Dae Woong Park; Dzuhri Radityo Utomo; Jong Phil Hong; Sang Gug Lee

doi:10.23919/VLSIC.2017.8008516

A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak G_max-core

Dae Woong Park
, Dzuhri Radityo Utomo
, Jong Phil Hong
, Sang Gug Lee

Dept. of Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

A dual-peak maximum achievable gain core design technique is proposed. It has been adopted into a 4-stage wideband amplifier. Implemented in a 65nm CMOS, the amplifier achieves 3dB bandwidth of 30GHz (230∼260GHz), gain of 12.4±1.5dB, and peak PAE of 1.6% while dissipating 23.8mW, which corresponds to the widest bandwidth and highest gain per stage among other reported CMOS amplifiers operating above 200GHz.

Original language	English
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C300-C301
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008516
State	Published - 10 Aug 2017
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: 5 Jun 2017 → 8 Jun 2017

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country/Territory	Japan
City	Kyoto
Period	5/06/17 → 8/06/17

Keywords

amplifier
broadband
CMOS
G

Access to Document

10.23919/VLSIC.2017.8008516

Cite this

Park, D. W., Utomo, D. R., Hong, J. P., & Lee, S. G. (2017). A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak G_max-core. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C300-C301). Article 8008516 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008516

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title = "A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core",

abstract = "A dual-peak maximum achievable gain core design technique is proposed. It has been adopted into a 4-stage wideband amplifier. Implemented in a 65nm CMOS, the amplifier achieves 3dB bandwidth of 30GHz (230∼260GHz), gain of 12.4±1.5dB, and peak PAE of 1.6\% while dissipating 23.8mW, which corresponds to the widest bandwidth and highest gain per stage among other reported CMOS amplifiers operating above 200GHz.",

keywords = "amplifier, broadband, CMOS, G",

author = "Park, \{Dae Woong\} and Utomo, \{Dzuhri Radityo\} and Hong, \{Jong Phil\} and Lee, \{Sang Gug\}",

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year = "2017",

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doi = "10.23919/VLSIC.2017.8008516",

language = "English",

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Park, DW, Utomo, DR, Hong, JP & Lee, SG 2017, A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak G_max-core. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008516, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. C300-C301, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 5/06/17. https://doi.org/10.23919/VLSIC.2017.8008516

A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak G_max-core. / Park, Dae Woong; Utomo, Dzuhri Radityo; Hong, Jong Phil et al.
2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C300-C301 8008516 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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