A 280-/300-GHz Three-Stage Amplifiers in 65-nm CMOS with 12-/9-dB Gain and 1.6/1.4% PAE while Dissipating 17.9 mW

Dae Woong Park, Dzuhri Radityo Utomo, Bao Huu Lam, Jong Phil Hong, Sang Gug Lee

Research output: Contribution to journalArticlepeer-review

40 Scopus citations

Abstract

This letter reports the design of terahertz amplifiers using the concept of maximum achievable gain ( $G-{\mathrm {max}})$ of a transistor embedded in a linear, lossless, reciprocal network. Implemented in a 65-nm CMOS, by adopting the optimized $G-{\mathrm {max}}$ -core, 280- and 300-GHz amplifiers achieve peak gain of 12 and 9 dB, peak power-added efficiency (PAE) of 1.6% and 1.4%, and gain per stage of 4 and 3 dB, respectively, while dissipating 17.9 mW, which is the best performance up to date in terms of operating frequency, gain per stage, and PAE in CMOS process.

Original languageEnglish
Article number8168414
Pages (from-to)79-81
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Volume28
Issue number1
DOIs
StatePublished - Jan 2018

Keywords

  • Amplifier
  • CMOS
  • Gmax
  • terahertz.

Fingerprint

Dive into the research topics of 'A 280-/300-GHz Three-Stage Amplifiers in 65-nm CMOS with 12-/9-dB Gain and 1.6/1.4% PAE while Dissipating 17.9 mW'. Together they form a unique fingerprint.

Cite this