A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS

Jae Won Nam; Young Deuk Jeon; Young Kyun Cho; Sang Gug Lee; Jong Kee Kwon

doi:10.1109/ESSCIRC.2009.5325946

A 2.85mW 0.12mm² 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS

Jae Won Nam, Young Deuk Jeon, Young Kyun Cho, Sang Gug Lee, Jong Kee Kwon

Electronic Engineering Program

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4dB, and 69.2dB at Nyquist input frequency with 20MS/s from a 1.0V supply, respectively. About 22% of OTA power dissipation is reduced without performance degradation and totally 2.85mW is consumed.

Original language	English
Title of host publication	ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
Pages	468-471
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2009.5325946
State	Published - 2009
Event	35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athens, Greece Duration: 14 Sep 2009 → 18 Sep 2009

Publication series

Name	ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Conference

Conference	35th European Solid-State Circuits Conference, ESSCIRC 2009
Country/Territory	Greece
City	Athens
Period	14/09/09 → 18/09/09

Access to Document

10.1109/ESSCIRC.2009.5325946

Cite this

Nam, J. W., Jeon, Y. D., Cho, Y. K., Lee, S. G., & Kwon, J. K. (2009). A 2.85mW 0.12mm² 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. In ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference (pp. 468-471). Article 5325946 (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2009.5325946

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title = "A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS",

abstract = "An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4dB, and 69.2dB at Nyquist input frequency with 20MS/s from a 1.0V supply, respectively. About 22\% of OTA power dissipation is reduced without performance degradation and totally 2.85mW is consumed.",

author = "Nam, \{Jae Won\} and Jeon, \{Young Deuk\} and Cho, \{Young Kyun\} and Lee, \{Sang Gug\} and Kwon, \{Jong Kee\}",

year = "2009",

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Nam, JW, Jeon, YD, Cho, YK, Lee, SG & Kwon, JK 2009, A 2.85mW 0.12mm² 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. in ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference., 5325946, ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference, pp. 468-471, 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14/09/09. https://doi.org/10.1109/ESSCIRC.2009.5325946

A 2.85mW 0.12mm² 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. / Nam, Jae Won; Jeon, Young Deuk; Cho, Young Kyun et al.
ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference. 2009. p. 468-471 5325946 (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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