A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS

Changhyuk Lee; Sok Kyu Lee; Sunghoon Ahn; Jinhaeng Lee; Wonsun Park; Yongdeok Cho; Chaekyu Jang; Chulwoo Yang; Sanghwa Chung; In Suk Yun; Byoungin Joo; Byoungkwan Jeong; Jeeyul Kim; Jeakwan Kwon; Hyunjong Jin; Yujong Noh; Jooyun Ha; Moonsoo Sung; Daeil Choi; Sanghwan Kim; Jeawon Choi; Taeho Jeon; Heejoung Park; Joong Seob Yang; Yo Hwan Koh

doi:10.1109/JSSC.2010.2084450

A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS

Changhyuk Lee, Sok Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, In Suk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jeakwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan KimJeawon Choi, Taeho Jeon, Heejoung Park, Joong Seob Yang, Yo Hwan Koh

Dept. of Electrical and Information Engineering

SK Corporation

Research output: Contribution to journal › Article › peer-review

32 Scopus citations

Abstract

Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 μs to 1250 μs. With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution.

Original language	English
Article number	5641590
Pages (from-to)	97-106
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	46
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2010.2084450
State	Published - Jan 2011

Keywords

Adaptive code selection
MSB re-program
NAND flash
cell-to-cell interference
moving read

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Lee, C., Lee, S. K., Ahn, S., Lee, J., Park, W., Cho, Y., Jang, C., Yang, C., Chung, S., Yun, I. S., Joo, B., Jeong, B., Kim, J., Kwon, J., Jin, H., Noh, Y., Ha, J., Sung, M., Choi, D., ... Koh, Y. H. (2011). A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS. IEEE Journal of Solid-State Circuits, 46(1), 97-106. Article 5641590. https://doi.org/10.1109/JSSC.2010.2084450

@article{6a8c530dfa0445d491f0e4905d7c5299,

title = "A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS",

abstract = "Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 μs to 1250 μs. With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5\% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution.",

keywords = "Adaptive code selection, MSB re-program, NAND flash, cell-to-cell interference, moving read",

author = "Changhyuk Lee and Lee, \{Sok Kyu\} and Sunghoon Ahn and Jinhaeng Lee and Wonsun Park and Yongdeok Cho and Chaekyu Jang and Chulwoo Yang and Sanghwa Chung and Yun, \{In Suk\} and Byoungin Joo and Byoungkwan Jeong and Jeeyul Kim and Jeakwan Kwon and Hyunjong Jin and Yujong Noh and Jooyun Ha and Moonsoo Sung and Daeil Choi and Sanghwan Kim and Jeawon Choi and Taeho Jeon and Heejoung Park and Yang, \{Joong Seob\} and Koh, \{Yo Hwan\}",

year = "2011",

month = jan,

doi = "10.1109/JSSC.2010.2084450",

language = "English",

volume = "46",

pages = "97--106",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

number = "1",

}

Lee, C, Lee, SK, Ahn, S, Lee, J, Park, W, Cho, Y, Jang, C, Yang, C, Chung, S, Yun, IS, Joo, B, Jeong, B, Kim, J, Kwon, J, Jin, H, Noh, Y, Ha, J, Sung, M, Choi, D, Kim, S, Choi, J, Jeon, T, Park, H, Yang, JS & Koh, YH 2011, 'A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS', IEEE Journal of Solid-State Circuits, vol. 46, no. 1, 5641590, pp. 97-106. https://doi.org/10.1109/JSSC.2010.2084450

TY - JOUR

T1 - A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS

AU - Lee, Changhyuk

AU - Lee, Sok Kyu

AU - Ahn, Sunghoon

AU - Lee, Jinhaeng

AU - Park, Wonsun

AU - Cho, Yongdeok

AU - Jang, Chaekyu

AU - Yang, Chulwoo

AU - Chung, Sanghwa

AU - Yun, In Suk

AU - Joo, Byoungin

AU - Jeong, Byoungkwan

AU - Kim, Jeeyul

AU - Kwon, Jeakwan

AU - Jin, Hyunjong

AU - Noh, Yujong

AU - Ha, Jooyun

AU - Sung, Moonsoo

AU - Choi, Daeil

AU - Kim, Sanghwan

AU - Choi, Jeawon

AU - Jeon, Taeho

AU - Park, Heejoung

AU - Yang, Joong Seob

AU - Koh, Yo Hwan

PY - 2011/1

Y1 - 2011/1

N2 - Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 μs to 1250 μs. With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution.

AB - Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 μs to 1250 μs. With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution.

KW - Adaptive code selection

KW - MSB re-program

KW - NAND flash

KW - cell-to-cell interference

KW - moving read

UR - http://www.scopus.com/inward/record.url?scp=78650858389&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2010.2084450

DO - 10.1109/JSSC.2010.2084450

M3 - Article

AN - SCOPUS:78650858389

SN - 0018-9200

VL - 46

SP - 97

EP - 106

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 1

M1 - 5641590

ER -

A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS

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Keywords

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