A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS

Changhyuk Lee; Sok Kyu Lee; Sunghoon Ahn; Jinhaeng Lee; Wonsun Park; Yongdeok Cho; Chaekyu Jang; Chulwoo Yang; Sanghwa Chung; In Suk Yun; Byoungin Joo; Byoungkwan Jeong; Jeeyul Kim; Jaekwan Kwon; Hyunjong Jin; Yujong Noh; Jooyun Ha; Moonsoo Sung; Daeil Choi; Sanghwan Kim; Jeawon Choi; Taeho Jeon; Joong Seob Yang; Yo Hwan Koh

doi:10.1109/ISSCC.2010.5433932

A 32Gb MLC NAND-flash memory with V_th-endurance-enhancing schemes in 32nm CMOS

Changhyuk Lee, Sok Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, In Suk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jaekwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan KimJeawon Choi, Taeho Jeon, Joong Seob Yang, Yo Hwan Koh

Dept. of Electrical and Information Engineering

SK Corporation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

23 Scopus citations

Abstract

As NAND flash memory market grows rapidly in various application such as USB devices, MP3 players, SSD, cellular phone, cameras, there is a strong requirement of high density and low cost devices. Two different approaches studied to meet these requirements are increasing data per cell and scaling down. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost [1,2]. However, these devices suffer from significant program performance degradation since tighter Vth distribution is required. On the other hand, scaling down can be a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome such as floating gate (FG) coupling and charge retention [3].

Original language	English
Title of host publication	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages	446-447
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2010.5433932
State	Published - 2010
Event	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States Duration: 7 Feb 2010 → 11 Feb 2010

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	53
ISSN (Print)	0193-6530

Conference

Conference	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
Country/Territory	United States
City	San Francisco, CA
Period	7/02/10 → 11/02/10

Access to Document

10.1109/ISSCC.2010.5433932

Cite this

Lee, C., Lee, S. K., Ahn, S., Lee, J., Park, W., Cho, Y., Jang, C., Yang, C., Chung, S., Yun, I. S., Joo, B., Jeong, B., Kim, J., Kwon, J., Jin, H., Noh, Y., Ha, J., Sung, M., Choi, D., ... Koh, Y. H. (2010). A 32Gb MLC NAND-flash memory with V_th-endurance-enhancing schemes in 32nm CMOS. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 446-447). Article 5433932 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5433932

@inproceedings{b26556bf8a1841a5ad24851212866683,

title = "A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS",

abstract = "As NAND flash memory market grows rapidly in various application such as USB devices, MP3 players, SSD, cellular phone, cameras, there is a strong requirement of high density and low cost devices. Two different approaches studied to meet these requirements are increasing data per cell and scaling down. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost [1,2]. However, these devices suffer from significant program performance degradation since tighter Vth distribution is required. On the other hand, scaling down can be a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome such as floating gate (FG) coupling and charge retention [3].",

author = "Changhyuk Lee and Lee, \{Sok Kyu\} and Sunghoon Ahn and Jinhaeng Lee and Wonsun Park and Yongdeok Cho and Chaekyu Jang and Chulwoo Yang and Sanghwa Chung and Yun, \{In Suk\} and Byoungin Joo and Byoungkwan Jeong and Jeeyul Kim and Jaekwan Kwon and Hyunjong Jin and Yujong Noh and Jooyun Ha and Moonsoo Sung and Daeil Choi and Sanghwan Kim and Jeawon Choi and Taeho Jeon and Yang, \{Joong Seob\} and Koh, \{Yo Hwan\}",

year = "2010",

doi = "10.1109/ISSCC.2010.5433932",

language = "English",

isbn = "9781424460342",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

pages = "446--447",

booktitle = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers",

note = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 ; Conference date: 07-02-2010 Through 11-02-2010",

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Lee, C, Lee, SK, Ahn, S, Lee, J, Park, W, Cho, Y, Jang, C, Yang, C, Chung, S, Yun, IS, Joo, B, Jeong, B, Kim, J, Kwon, J, Jin, H, Noh, Y, Ha, J, Sung, M, Choi, D, Kim, S, Choi, J, Jeon, T, Yang, JS & Koh, YH 2010, A 32Gb MLC NAND-flash memory with V_th-endurance-enhancing schemes in 32nm CMOS. in 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers., 5433932, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 53, pp. 446-447, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 7/02/10. https://doi.org/10.1109/ISSCC.2010.5433932

A 32Gb MLC NAND-flash memory with V_th-endurance-enhancing schemes in 32nm CMOS. / Lee, Changhyuk; Lee, Sok Kyu; Ahn, Sunghoon et al.
2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 446-447 5433932 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS

AU - Lee, Changhyuk

AU - Lee, Sok Kyu

AU - Ahn, Sunghoon

AU - Lee, Jinhaeng

AU - Park, Wonsun

AU - Cho, Yongdeok

AU - Jang, Chaekyu

AU - Yang, Chulwoo

AU - Chung, Sanghwa

AU - Yun, In Suk

AU - Joo, Byoungin

AU - Jeong, Byoungkwan

AU - Kim, Jeeyul

AU - Kwon, Jaekwan

AU - Jin, Hyunjong

AU - Noh, Yujong

AU - Ha, Jooyun

AU - Sung, Moonsoo

AU - Choi, Daeil

AU - Kim, Sanghwan

AU - Choi, Jeawon

AU - Jeon, Taeho

AU - Yang, Joong Seob

AU - Koh, Yo Hwan

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AB - As NAND flash memory market grows rapidly in various application such as USB devices, MP3 players, SSD, cellular phone, cameras, there is a strong requirement of high density and low cost devices. Two different approaches studied to meet these requirements are increasing data per cell and scaling down. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost [1,2]. However, these devices suffer from significant program performance degradation since tighter Vth distribution is required. On the other hand, scaling down can be a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome such as floating gate (FG) coupling and charge retention [3].

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M3 - Conference contribution

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SN - 9781424460342

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

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BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers

T2 - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010

Y2 - 7 February 2010 through 11 February 2010

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Lee C, Lee SK, Ahn S, Lee J, Park W, Cho Y et al. A 32Gb MLC NAND-flash memory with V_th-endurance-enhancing schemes in 32nm CMOS. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 446-447. 5433932. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2010.5433932