A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control

A qubit-control waveform generator utilizing a 4-channel time-interleaved ΔΣ DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a ΔΣ modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed ΔΣ DAC consumes 256.04 mW of power, and the core area is 0.11mm². The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.