A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer

Kyung Sik Choi; Keun Mok Kim; Jinho Ko; Sang Gug Lee

doi:10.1109/A-SSCC48613.2020.9336141

A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer

Kyung Sik Choi, Keun Mok Kim, Jinho Ko, Sang Gug Lee

Electronic Engineering Program

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

This paper presents a 915 MHz binary frequency-shift keying (BFSK) internet of things (IoT) transmitter (TX) utilizing a frequency tripler driven by duty and phase calibrated signal. The proposed frequency tripling method is adopted to suppress the unwanted harmonic spurs generated from the conventional frequency tripler followed by a class-D power amplifier (PA), relaxing the requirement for the harmonic filtering at the PA output. Implemented in a 55 nm CMOS, the proposed TX achieves the output power of 5 dBm and efficiency of 30.6% with an on-chip PA matching network (MN) while dissipating a dc power of 210 μW in the synthesizer.

Original language	English
Title of host publication	2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728184364
DOIs	https://doi.org/10.1109/A-SSCC48613.2020.9336141
State	Published - 9 Nov 2020
Event	16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 - Virtual, Hiroshima, Japan Duration: 9 Nov 2020 → 11 Nov 2020

Publication series

Name	2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

Conference

Conference	16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
Country/Territory	Japan
City	Virtual, Hiroshima
Period	9/11/20 → 11/11/20

Keywords

Class-D power amplifier
CMOS
Duty calibration
Frequency tripler
Low-power
Transmitter

Access to Document

10.1109/A-SSCC48613.2020.9336141

Cite this

Choi, K. S., Kim, K. M., Ko, J., & Lee, S. G. (2020). A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. In 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 Article 9336141 (2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC48613.2020.9336141

Choi, Kyung Sik ; Kim, Keun Mok ; Ko, Jinho et al. / A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020).

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abstract = "This paper presents a 915 MHz binary frequency-shift keying (BFSK) internet of things (IoT) transmitter (TX) utilizing a frequency tripler driven by duty and phase calibrated signal. The proposed frequency tripling method is adopted to suppress the unwanted harmonic spurs generated from the conventional frequency tripler followed by a class-D power amplifier (PA), relaxing the requirement for the harmonic filtering at the PA output. Implemented in a 55 nm CMOS, the proposed TX achieves the output power of 5 dBm and efficiency of 30.6\% with an on-chip PA matching network (MN) while dissipating a dc power of 210 μW in the synthesizer.",

keywords = "Class-D power amplifier, CMOS, Duty calibration, Frequency tripler, Low-power, Transmitter",

author = "Choi, \{Kyung Sik\} and Kim, \{Keun Mok\} and Jinho Ko and Lee, \{Sang Gug\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 ; Conference date: 09-11-2020 Through 11-11-2020",

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Choi, KS, Kim, KM, Ko, J & Lee, SG 2020, A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. in 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020., 9336141, 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Institute of Electrical and Electronics Engineers Inc., 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual, Hiroshima, Japan, 9/11/20. https://doi.org/10.1109/A-SSCC48613.2020.9336141

A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. / Choi, Kyung Sik; Kim, Keun Mok; Ko, Jinho et al.
2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9336141 (2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lee, Sang Gug

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N2 - This paper presents a 915 MHz binary frequency-shift keying (BFSK) internet of things (IoT) transmitter (TX) utilizing a frequency tripler driven by duty and phase calibrated signal. The proposed frequency tripling method is adopted to suppress the unwanted harmonic spurs generated from the conventional frequency tripler followed by a class-D power amplifier (PA), relaxing the requirement for the harmonic filtering at the PA output. Implemented in a 55 nm CMOS, the proposed TX achieves the output power of 5 dBm and efficiency of 30.6% with an on-chip PA matching network (MN) while dissipating a dc power of 210 μW in the synthesizer.

AB - This paper presents a 915 MHz binary frequency-shift keying (BFSK) internet of things (IoT) transmitter (TX) utilizing a frequency tripler driven by duty and phase calibrated signal. The proposed frequency tripling method is adopted to suppress the unwanted harmonic spurs generated from the conventional frequency tripler followed by a class-D power amplifier (PA), relaxing the requirement for the harmonic filtering at the PA output. Implemented in a 55 nm CMOS, the proposed TX achieves the output power of 5 dBm and efficiency of 30.6% with an on-chip PA matching network (MN) while dissipating a dc power of 210 μW in the synthesizer.

KW - Class-D power amplifier

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KW - Duty calibration

KW - Frequency tripler

KW - Low-power

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Choi KS, Kim KM, Ko J, Lee SG. A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. In 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9336141. (2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020). doi: 10.1109/A-SSCC48613.2020.9336141

A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μw ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer

Abstract

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Keywords

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