A 5.5-dBm, 31.9% Efficiency 915-MHz Transmitter Employing Frequency Tripler and 207-μW Synthesizer

Kyung Sik Choi; Keun Mok Kim; Su Bin Kim; Byeong Hun Yun; Jinho Ko; Jusung Kim; Sang Gug Lee

doi:10.1109/LMWC.2019.2953208

A 5.5-dBm, 31.9% Efficiency 915-MHz Transmitter Employing Frequency Tripler and 207-μW Synthesizer

Kyung Sik Choi, Keun Mok Kim, Su Bin Kim, Byeong Hun Yun, Jinho Ko, Jusung Kim, Sang Gug Lee

Electronic Engineering Program

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

A 915-MHz binary frequency-shift keying (BFSK) transmitter is proposed in this letter. The proposed transmitter architecture allows relaxing the frequency-tuning requirement of the conventional Internet of Things transceiver by the frequency-tripling signal-path topology. The tuning-range requirement is significantly improved down to 4% with the proposed signaling scheme, and this results in the ultralow-power synthesizer implementation. The proposed frequency tripler provides good spur rejection performance, and the adoption of a class-D switching power amplifier (PA) further improves the efficiency of the BFSK transmitter. Implemented in a 55-nm CMOS technology, the proposed transmitter achieves the output power of 5.5 dBm and 31.9% efficiency with only 207 μW of power consumption from the synthesizer.

Original language	English
Article number	8928561
Pages (from-to)	90-93
Number of pages	4
Journal	IEEE Microwave and Wireless Components Letters
Volume	30
Issue number	1
DOIs	https://doi.org/10.1109/LMWC.2019.2953208
State	Published - Jan 2020

Keywords

Binary frequency-shift keying (BFSK)
CMOS
frequency tripler
transmitter
ultralow-power (ULP)

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10.1109/LMWC.2019.2953208

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title = "A 5.5-dBm, 31.9% Efficiency 915-MHz Transmitter Employing Frequency Tripler and 207-μW Synthesizer",

abstract = "A 915-MHz binary frequency-shift keying (BFSK) transmitter is proposed in this letter. The proposed transmitter architecture allows relaxing the frequency-tuning requirement of the conventional Internet of Things transceiver by the frequency-tripling signal-path topology. The tuning-range requirement is significantly improved down to 4% with the proposed signaling scheme, and this results in the ultralow-power synthesizer implementation. The proposed frequency tripler provides good spur rejection performance, and the adoption of a class-D switching power amplifier (PA) further improves the efficiency of the BFSK transmitter. Implemented in a 55-nm CMOS technology, the proposed transmitter achieves the output power of 5.5 dBm and 31.9% efficiency with only 207 μW of power consumption from the synthesizer.",

keywords = "Binary frequency-shift keying (BFSK), CMOS, frequency tripler, transmitter, ultralow-power (ULP)",

author = "Choi, {Kyung Sik} and Kim, {Keun Mok} and Kim, {Su Bin} and Yun, {Byeong Hun} and Jinho Ko and Jusung Kim and Lee, {Sang Gug}",

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AU - Yun, Byeong Hun

AU - Ko, Jinho

AU - Kim, Jusung

AU - Lee, Sang Gug

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AB - A 915-MHz binary frequency-shift keying (BFSK) transmitter is proposed in this letter. The proposed transmitter architecture allows relaxing the frequency-tuning requirement of the conventional Internet of Things transceiver by the frequency-tripling signal-path topology. The tuning-range requirement is significantly improved down to 4% with the proposed signaling scheme, and this results in the ultralow-power synthesizer implementation. The proposed frequency tripler provides good spur rejection performance, and the adoption of a class-D switching power amplifier (PA) further improves the efficiency of the BFSK transmitter. Implemented in a 55-nm CMOS technology, the proposed transmitter achieves the output power of 5.5 dBm and 31.9% efficiency with only 207 μW of power consumption from the synthesizer.

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A 5.5-dBm, 31.9% Efficiency 915-MHz Transmitter Employing Frequency Tripler and 207-μW Synthesizer

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Keywords

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