A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Chang Kyo Lee; Minsu Ahn; Daesik Moon; Kiho Kim; Yoon Joo Eom; Won Young Lee; Jongmin Kim; Sanghyuk Yoon; Baekkyu Choi; Seokhong Kwon; Joon Young Park; Seung Jun Bae; Yong Cheol Bae; Jung Hwan Choi; Seong Jin Jang; Gyoyoung Jin

doi:10.1109/VLSIC.2015.7231254

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Chang Kyo Lee, Minsu Ahn, Daesik Moon, Kiho Kim, Yoon Joo Eom, Won Young Lee, Jongmin Kim, Sanghyuk Yoon, Baekkyu Choi, Seokhong Kwon, Joon Young Park, Seung Jun Bae, Yong Cheol Bae, Jung Hwan Choi, Seong Jin Jang, Gyoyoung Jin

Media IT Engineering Program

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 % enhancement of I/O power efficiency compared to that of the LPDDR4.

Original language	English
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C182-C183
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231254
State	Published - 31 Aug 2015
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: 17 Jun 2015 → 19 Jun 2015

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Conference

Conference	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	17/06/15 → 19/06/15

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10.1109/VLSIC.2015.7231254

Cite this

Lee, C. K., Ahn, M., Moon, D., Kim, K., Eom, Y. J., Lee, W. Y., Kim, J., Yoon, S., Choi, B., Kwon, S., Park, J. Y., Bae, S. J., Bae, Y. C., Choi, J. H., Jang, S. J., & Jin, G. (2015). A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C182-C183). Article 7231254 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231254

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title = "A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface",

abstract = "A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 \% enhancement of I/O power efficiency compared to that of the LPDDR4.",

author = "Lee, \{Chang Kyo\} and Minsu Ahn and Daesik Moon and Kiho Kim and Eom, \{Yoon Joo\} and Lee, \{Won Young\} and Jongmin Kim and Sanghyuk Yoon and Baekkyu Choi and Seokhong Kwon and Park, \{Joon Young\} and Bae, \{Seung Jun\} and Bae, \{Yong Cheol\} and Choi, \{Jung Hwan\} and Jang, \{Seong Jin\} and Gyoyoung Jin",

note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 ; Conference date: 17-06-2015 Through 19-06-2015",

year = "2015",

month = aug,

day = "31",

doi = "10.1109/VLSIC.2015.7231254",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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Lee, CK, Ahn, M, Moon, D, Kim, K, Eom, YJ, Lee, WY, Kim, J, Yoon, S, Choi, B, Kwon, S, Park, JY, Bae, SJ, Bae, YC, Choi, JH, Jang, SJ & Jin, G 2015, A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231254, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C182-C183, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 17/06/15. https://doi.org/10.1109/VLSIC.2015.7231254

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. / Lee, Chang Kyo; Ahn, Minsu; Moon, Daesik et al.
2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C182-C183 7231254 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Eom, Yoon Joo

AU - Lee, Won Young

AU - Kim, Jongmin

AU - Yoon, Sanghyuk

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AU - Kwon, Seokhong

AU - Park, Joon Young

AU - Bae, Seung Jun

AU - Bae, Yong Cheol

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AU - Jin, Gyoyoung

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AB - A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 % enhancement of I/O power efficiency compared to that of the LPDDR4.

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Lee CK, Ahn M, Moon D, Kim K, Eom YJ, Lee WY et al. A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C182-C183. 7231254. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2015.7231254

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

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