TY - JOUR
T1 - A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration
AU - Choi, Kyung Sik
AU - Kim, Keun Mok
AU - Ko, Jinho
AU - Lee, Sang Gug
N1 - Publisher Copyright:
© 1966-2012 IEEE.
PY - 2022/11/1
Y1 - 2022/11/1
N2 - A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- ${Q}$. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 $\mu \text{W}$ in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below -41 dBm with the worst harmonic distortion of -48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.
AB - A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- ${Q}$. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 $\mu \text{W}$ in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below -41 dBm with the worst harmonic distortion of -48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.
KW - Binary frequency-shift keying (BFSK)
KW - class-D
KW - CMOS
KW - duty-cycle calibration
KW - Internet-of-Things (IoT)
KW - low-power
KW - power amplifier (PA)
KW - transmitter (TX)
UR - http://www.scopus.com/inward/record.url?scp=85132517213&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2022.3172467
DO - 10.1109/JSSC.2022.3172467
M3 - Article
AN - SCOPUS:85132517213
SN - 0018-9200
VL - 57
SP - 3336
EP - 3347
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 11
ER -