A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR ADC in 65nm CMOS

Young Deuk Jeon; Young Kyun Cho; Jae Won Nam; Kwi Dong Kim; Woo Yol Lee; Kuk Tae Hong; Jong Kee Kwon

doi:10.1109/CICC.2010.5617457

A 9.15mW 0.22mm² 10b 204MS/s Pipelined SAR ADC in 65nm CMOS

Young Deuk Jeon, Young Kyun Cho, Jae Won Nam, Kwi Dong Kim, Woo Yol Lee, Kuk Tae Hong, Jong Kee Kwon

Electronic Engineering Program

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

41 Scopus citations

Abstract

This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm² and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step.

Original language	English
Title of host publication	IEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs	https://doi.org/10.1109/CICC.2010.5617457
State	Published - 2010
Event	32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States Duration: 19 Sep 2010 → 22 Sep 2010

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Country/Territory	United States
City	San Jose, CA
Period	19/09/10 → 22/09/10

Access to Document

10.1109/CICC.2010.5617457

Cite this

@inproceedings{74bd9d55a981411b82b7650f8d70af2b,

title = "A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR ADC in 65nm CMOS",

abstract = "This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm2 and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step.",

author = "Jeon, \{Young Deuk\} and Cho, \{Young Kyun\} and Nam, \{Jae Won\} and Kim, \{Kwi Dong\} and Lee, \{Woo Yol\} and Hong, \{Kuk Tae\} and Kwon, \{Jong Kee\}",

year = "2010",

doi = "10.1109/CICC.2010.5617457",

language = "English",

isbn = "9781424457588",

series = "Proceedings of the Custom Integrated Circuits Conference",

booktitle = "IEEE Custom Integrated Circuits Conference 2010, CICC 2010",

note = "32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 ; Conference date: 19-09-2010 Through 22-09-2010",

}

Jeon, YD, Cho, YK, Nam, JW, Kim, KD, Lee, WY, Hong, KT & Kwon, JK 2010, A 9.15mW 0.22mm² 10b 204MS/s Pipelined SAR ADC in 65nm CMOS. in IEEE Custom Integrated Circuits Conference 2010, CICC 2010., 5617457, Proceedings of the Custom Integrated Circuits Conference, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, San Jose, CA, United States, 19/09/10. https://doi.org/10.1109/CICC.2010.5617457

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T1 - A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR ADC in 65nm CMOS

AU - Jeon, Young Deuk

AU - Cho, Young Kyun

AU - Nam, Jae Won

AU - Kim, Kwi Dong

AU - Lee, Woo Yol

AU - Hong, Kuk Tae

AU - Kwon, Jong Kee

PY - 2010

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N2 - This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm2 and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step.

AB - This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm2 and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step.

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