TY - GEN
T1 - A Charge Balanced Neural Stimulator Using Chopped Anodic Pulse Control
AU - Son, Jin Young
AU - Cha, Hyouk Kyu
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/6
Y1 - 2019/6
N2 - This paper presents a novel neural stimulator integrated circuit (IC) that utilizes a chopped pulse waveform for higher power efficiency and active charge balancing. The proposed IC, designed using 0.18mu m standard CMOS process, consists of electrical stimulator circuit and active charge balancing circuit. Transistor stacking technique is employed in the stimulator circuit to protect the output current driver devices and charge balancing devices from high voltage stress. The proposed active charge balancing circuit uses a very simple digital logic circuit that consists of comparator and D-latch which can perform safe charge balancing by using the chopped anodic pulse control.
AB - This paper presents a novel neural stimulator integrated circuit (IC) that utilizes a chopped pulse waveform for higher power efficiency and active charge balancing. The proposed IC, designed using 0.18mu m standard CMOS process, consists of electrical stimulator circuit and active charge balancing circuit. Transistor stacking technique is employed in the stimulator circuit to protect the output current driver devices and charge balancing devices from high voltage stress. The proposed active charge balancing circuit uses a very simple digital logic circuit that consists of comparator and D-latch which can perform safe charge balancing by using the chopped anodic pulse control.
KW - active charge balancing
KW - chopped pulse
KW - CMOS
KW - electrical stimulation
KW - implantable biomedical devices
UR - https://www.scopus.com/pages/publications/85071454339
U2 - 10.1109/ITC-CSCC.2019.8793339
DO - 10.1109/ITC-CSCC.2019.8793339
M3 - Conference contribution
AN - SCOPUS:85071454339
T3 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
BT - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
Y2 - 23 June 2019 through 26 June 2019
ER -