A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications

Hyouk Kyu Cha; Seong Sik Song; Hong Teuk Kim; Kwyro Lee

doi:10.1109/LMWC.2008.2002463

A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications

Hyouk Kyu Cha, Seong Sik Song, Hong Teuk Kim, Kwyro Lee

Dept. of Electrical and Information Engineering

Research output: Contribution to journal › Article › peer-review

29 Scopus citations

Abstract

A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-μm CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.

Original language	English
Article number	4624625
Pages (from-to)	617-619
Number of pages	3
Journal	IEEE Microwave and Wireless Components Letters
Volume	18
Issue number	9
DOIs	https://doi.org/10.1109/LMWC.2008.2002463
State	Published - Sep 2008

Keywords

ATSC
CMOS
Digital TV tuner
Harmonic rejection mixer
Mismatch calibration

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10.1109/LMWC.2008.2002463

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@article{61167305f355498db279fcc09f064838,

title = "A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications",

abstract = "A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-μm CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.",

keywords = "ATSC, CMOS, Digital TV tuner, Harmonic rejection mixer, Mismatch calibration",

author = "Cha, \{Hyouk Kyu\} and Song, \{Seong Sik\} and Kim, \{Hong Teuk\} and Kwyro Lee",

year = "2008",

month = sep,

doi = "10.1109/LMWC.2008.2002463",

language = "English",

volume = "18",

pages = "617--619",

journal = "IEEE Microwave and Wireless Components Letters",

issn = "1531-1309",

number = "9",

}

TY - JOUR

T1 - A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications

AU - Cha, Hyouk Kyu

AU - Song, Seong Sik

AU - Kim, Hong Teuk

AU - Lee, Kwyro

PY - 2008/9

Y1 - 2008/9

N2 - A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-μm CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.

AB - A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-μm CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.

KW - ATSC

KW - CMOS

KW - Digital TV tuner

KW - Harmonic rejection mixer

KW - Mismatch calibration

UR - https://www.scopus.com/pages/publications/52049097292

U2 - 10.1109/LMWC.2008.2002463

DO - 10.1109/LMWC.2008.2002463

M3 - Article

AN - SCOPUS:52049097292

SN - 1531-1309

VL - 18

SP - 617

EP - 619

JO - IEEE Microwave and Wireless Components Letters

JF - IEEE Microwave and Wireless Components Letters

IS - 9

M1 - 4624625

ER -

A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications

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