A Comparative Study of MOS-Controlled and Capacitor-Controlled Charge-Pump based Feed-Forward Equalizers for High-Speed and Low-Power Memory Interfaces

In low-power memory interfaces, the TX (transmitter) typically employs a FFE (Feed-Forward Equalizer) to enable high-speed operation. Conventional FFEs suffer from issues such as reduced eye margin and increased unnecessary power consumption. To address these problems, previous research proposed a CP FFE (Charge-Pump based FFE) technique. However, since the FFE weight was controlled through the Ron (on-resistance) of the MOS transistors composing the charge pump, this approach exhibited degraded jitter characteristics due to the nonlinear nature of Ron. This paper proposes a Cap-Controlled CP FFE architecture that adjusts the FFE weight using parallel capacitors to overcome these limitations. Simulation results in a 65-nm CMOS process demonstrate that the proposed Cap-Controlled structure achieves more stable equalization and improved jitter performance compared to the conventional MOS-Controlled architecture under the same channel loss conditions.