A Delta-Readout Scheme for Low-Power CMOS Image Sensors with Multi-Column-Parallel SAR ADCs

Hyeon June Kim; Sun Il Hwang; Ji Wook Kwon; Dong Hwan Jin; Byoung Soo Choi; Sang Gwon Lee; Jong Ho Park; Jang Kyoo Shin; Seung Tak Ryu

doi:10.1109/JSSC.2016.2581819

A Delta-Readout Scheme for Low-Power CMOS Image Sensors with Multi-Column-Parallel SAR ADCs

Hyeon June Kim, Sun Il Hwang, Ji Wook Kwon, Dong Hwan Jin, Byoung Soo Choi, Sang Gwon Lee, Jong Ho Park, Jang Kyoo Shin, Seung Tak Ryu

Dept. of Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

55 Scopus citations

Abstract

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout (Δ-readout) scheme reads the signal difference between two pixels located next to each other (Δ_pixel) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by theΔ-window checking, the proposedΔ-readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a 0.18μm 1P4M CIS process with a 4.4μm pixel pitch, where each single ADC occupies an area of 70 μm × 500 μm. The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.

Original language	English
Article number	7526314
Pages (from-to)	2262-2273
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	51
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2016.2581819
State	Published - Oct 2016

Keywords

CMOS image sensor (CIS)
delta-readout (Δ-readout) scheme
image-dependent power savings
multi-columnparallel (MCP)
successive-approximation register analog-todigital converter (SAR ADC)

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10.1109/JSSC.2016.2581819

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title = "A Delta-Readout Scheme for Low-Power CMOS Image Sensors with Multi-Column-Parallel SAR ADCs",

abstract = "This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout (Δ-readout) scheme reads the signal difference between two pixels located next to each other (Δpixel) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by theΔ-window checking, the proposedΔ-readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a 0.18μm 1P4M CIS process with a 4.4μm pixel pitch, where each single ADC occupies an area of 70 μm × 500 μm. The measurement results of the implemented prototype CIS showed a maximum power-saving of 26\% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.",

keywords = "CMOS image sensor (CIS), delta-readout (Δ-readout) scheme, image-dependent power savings, multi-columnparallel (MCP), successive-approximation register analog-todigital converter (SAR ADC)",

author = "Kim, \{Hyeon June\} and Hwang, \{Sun Il\} and Kwon, \{Ji Wook\} and Jin, \{Dong Hwan\} and Choi, \{Byoung Soo\} and Lee, \{Sang Gwon\} and Park, \{Jong Ho\} and Shin, \{Jang Kyoo\} and Ryu, \{Seung Tak\}",

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AU - Hwang, Sun Il

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AU - Jin, Dong Hwan

AU - Choi, Byoung Soo

AU - Lee, Sang Gwon

AU - Park, Jong Ho

AU - Shin, Jang Kyoo

AU - Ryu, Seung Tak

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AB - This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout (Δ-readout) scheme reads the signal difference between two pixels located next to each other (Δpixel) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by theΔ-window checking, the proposedΔ-readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a 0.18μm 1P4M CIS process with a 4.4μm pixel pitch, where each single ADC occupies an area of 70 μm × 500 μm. The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.

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A Delta-Readout Scheme for Low-Power CMOS Image Sensors with Multi-Column-Parallel SAR ADCs

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