A digital clock and data strobe aligner for write calibration of dynamic random access memory

This paper proposes a digital clock and data strobe aligner for write calibration of dynamic random access memory (DRAM). The edge recognizer determines the input phase skew between a falling edge of clock and a rising edge of data strobe (DQS) signal to maximize setup and hold margins of DQS and clock synchronization. According to experimental results, the proposed circuit achieves the minimum and maximum output skews are −6.9 ps and 7.5 ps when DQS skews of ±227 ps are applied. The chip has been fabricated in 180 nm CMOS technology and the active chip area is 0.091 mm².