TY - JOUR
T1 - A Dual-Exposure Readout Integrated Circuit for Dynamic Range Enhancement in SWIR Image Sensors
AU - Park, Min Jun
AU - Lee, Dong Yeon
AU - Yoon, Jung Won
AU - Jeon, Ji Yeon
AU - Lee, Sang Jun
AU - Kim, Hyeon June
N1 - Publisher Copyright:
© 2001-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - This article presents a prototype short-wave infrared (SWIR) image sensor with a dual-exposure readout technique, achieving wide dynamic range (WDR) while maintaining a compact pixel design. The proposed dual-exposure readout technique enhances dynamic range (DR) without increasing the integration capacitor of unit pixel, addressing the tradeoff between pixel miniaturization and DR expansion in SWIR image sensors. This method allows the sensor to capture both low- and high-intensity signals, preventing saturation in bright regions while maintaining sensitivity to weak signals. The proposed readout integrated circuit (ROIC), implemented in a 0.18-µm CMOS process, features a 128 x 128 pixel array with a 20-µm pixel pitch, utilizing a capacitive transimpedance amplifier (CTIA) front end for enhanced signal fidelity. In addition, the sensor exhibits a low readout noise of 86.83 µV rms and operates with a power consumption of 42.24 mW, making it suitable for low-power, high-speed SWIR imaging applications. These results confirm that the proposed architecture provides a scalable, power-efficient solution for next-generation SWIR imaging systems.
AB - This article presents a prototype short-wave infrared (SWIR) image sensor with a dual-exposure readout technique, achieving wide dynamic range (WDR) while maintaining a compact pixel design. The proposed dual-exposure readout technique enhances dynamic range (DR) without increasing the integration capacitor of unit pixel, addressing the tradeoff between pixel miniaturization and DR expansion in SWIR image sensors. This method allows the sensor to capture both low- and high-intensity signals, preventing saturation in bright regions while maintaining sensitivity to weak signals. The proposed readout integrated circuit (ROIC), implemented in a 0.18-µm CMOS process, features a 128 x 128 pixel array with a 20-µm pixel pitch, utilizing a capacitive transimpedance amplifier (CTIA) front end for enhanced signal fidelity. In addition, the sensor exhibits a low readout noise of 86.83 µV rms and operates with a power consumption of 42.24 mW, making it suitable for low-power, high-speed SWIR imaging applications. These results confirm that the proposed architecture provides a scalable, power-efficient solution for next-generation SWIR imaging systems.
KW - Capacitive transimpedance amplifier (CTIA)-based readout integrated circuit (ROIC)
KW - dual-exposure readout
KW - short-wave infrared (SWIR) detectors
KW - SWIR image sensor
UR - https://www.scopus.com/pages/publications/105012226753
U2 - 10.1109/JSEN.2025.3587528
DO - 10.1109/JSEN.2025.3587528
M3 - Article
AN - SCOPUS:105012226753
SN - 1530-437X
VL - 25
SP - 32546
EP - 32555
JO - IEEE Sensors Journal
JF - IEEE Sensors Journal
IS - 17
ER -