Abstract
In this paper, a duty cycle corrector (DCC) with a dual loop low pass filter (DLLPF) has been proposed to improve correction time and noise characteristics. It shows that the correction time is 4.25 times faster and the fluctuation is 7.86 times lower compared to a conventional DCC with a typical low pass filter. The proposed DCC has been fabricated in a 0.18-μm CMOS technology with a supply voltage of 1.8 V within area of 0.03 mm2. The experimental results show that the operation range is from 800 MHz to 1.6 GHz for input duty cycle variation within 25 % and 75 %. At the 1.6 GHz operating frequency, the measured root-mean-square and peak-to-peak jitters are 1.66 ps and 12.69 ps, respectively.
| Original language | English |
|---|---|
| Article number | 154568 |
| Journal | AEU - International Journal of Electronics and Communications |
| Volume | 162 |
| DOIs | |
| State | Published - Apr 2023 |
Keywords
- Double data rate (DDR)
- Duty cycle
- Duty cycle corrector (DCC)
- Loop filter