A Fast Locking Duty Cycle Corrector with High Accuracy

Eun Young Jung; Won Young Lee

doi:10.1109/ISOCC50952.2020.9332963

A Fast Locking Duty Cycle Corrector with High Accuracy

Eun Young Jung, Won Young Lee

Media IT Engineering Program

Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents a fast locking duty cycle corrector (DCC) with high accuracy for mobile memory. The DCC has a low pass filter to convert detected values by duty cycle detector (DCD) into offset voltages and transmit the voltages to duty cycle adjuster (DCA) to adjust common mode voltages. The low pass filter has a tradeoff between correction time and accuracy depending on the capacitor value. The dual loop low pass filter (DLLPF) has been proposed for high accuracy and fast correction time. The locking time is 1.89 times faster and the fluctuation is 9.21 times lower compared to conventional low pass filter. The circuit is implemented in CMOS 0.18-μm technology using 1.8-V supply. The output duty cycle is corrected to 50±1% over the input duty cycle range of 20-80% for 1.6GHz.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	45-46
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332963
State	Published - 21 Oct 2020
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 21 Oct 2020 → 24 Oct 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	21/10/20 → 24/10/20

Keywords

accuracy
correction time
DCC

Access to Document

10.1109/ISOCC50952.2020.9332963

Cite this

@inproceedings{e37bfc4b1c5b4df3a335eb6be7be94c1,

title = "A Fast Locking Duty Cycle Corrector with High Accuracy",

abstract = "This paper presents a fast locking duty cycle corrector (DCC) with high accuracy for mobile memory. The DCC has a low pass filter to convert detected values by duty cycle detector (DCD) into offset voltages and transmit the voltages to duty cycle adjuster (DCA) to adjust common mode voltages. The low pass filter has a tradeoff between correction time and accuracy depending on the capacitor value. The dual loop low pass filter (DLLPF) has been proposed for high accuracy and fast correction time. The locking time is 1.89 times faster and the fluctuation is 9.21 times lower compared to conventional low pass filter. The circuit is implemented in CMOS 0.18-μm technology using 1.8-V supply. The output duty cycle is corrected to 50±1\% over the input duty cycle range of 20-80\% for 1.6GHz.",

keywords = "accuracy, correction time, DCC",

author = "Jung, \{Eun Young\} and Lee, \{Won Young\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

month = oct,

day = "21",

doi = "10.1109/ISOCC50952.2020.9332963",

language = "English",

series = "Proceedings - International SoC Design Conference, ISOCC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "45--46",

booktitle = "Proceedings - International SoC Design Conference, ISOCC 2020",

}

Jung, EY & Lee, WY 2020, A Fast Locking Duty Cycle Corrector with High Accuracy. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332963, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 45-46, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 21/10/20. https://doi.org/10.1109/ISOCC50952.2020.9332963

A Fast Locking Duty Cycle Corrector with High Accuracy. / Jung, Eun Young; Lee, Won Young.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 45-46 9332963 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Fast Locking Duty Cycle Corrector with High Accuracy

AU - Jung, Eun Young

AU - Lee, Won Young

PY - 2020/10/21

Y1 - 2020/10/21

N2 - This paper presents a fast locking duty cycle corrector (DCC) with high accuracy for mobile memory. The DCC has a low pass filter to convert detected values by duty cycle detector (DCD) into offset voltages and transmit the voltages to duty cycle adjuster (DCA) to adjust common mode voltages. The low pass filter has a tradeoff between correction time and accuracy depending on the capacitor value. The dual loop low pass filter (DLLPF) has been proposed for high accuracy and fast correction time. The locking time is 1.89 times faster and the fluctuation is 9.21 times lower compared to conventional low pass filter. The circuit is implemented in CMOS 0.18-μm technology using 1.8-V supply. The output duty cycle is corrected to 50±1% over the input duty cycle range of 20-80% for 1.6GHz.

AB - This paper presents a fast locking duty cycle corrector (DCC) with high accuracy for mobile memory. The DCC has a low pass filter to convert detected values by duty cycle detector (DCD) into offset voltages and transmit the voltages to duty cycle adjuster (DCA) to adjust common mode voltages. The low pass filter has a tradeoff between correction time and accuracy depending on the capacitor value. The dual loop low pass filter (DLLPF) has been proposed for high accuracy and fast correction time. The locking time is 1.89 times faster and the fluctuation is 9.21 times lower compared to conventional low pass filter. The circuit is implemented in CMOS 0.18-μm technology using 1.8-V supply. The output duty cycle is corrected to 50±1% over the input duty cycle range of 20-80% for 1.6GHz.

KW - accuracy

KW - correction time

KW - DCC

UR - https://www.scopus.com/pages/publications/85100789559

U2 - 10.1109/ISOCC50952.2020.9332963

DO - 10.1109/ISOCC50952.2020.9332963

M3 - Conference contribution

AN - SCOPUS:85100789559

T3 - Proceedings - International SoC Design Conference, ISOCC 2020

SP - 45

EP - 46

BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International System-on-Chip Design Conference, ISOCC 2020

Y2 - 21 October 2020 through 24 October 2020

ER -

A Fast Locking Duty Cycle Corrector with High Accuracy

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this