A generic network interface architecture for a Networked Processor Array (NePA)

Seung Eun Lee; Jun Ho Bahn; Yoon Seok Yang; Nader Bagherzadeh

doi:10.1007/978-3-540-78153-0_19

A generic network interface architecture for a Networked Processor Array (NePA)

Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh

Electronic Engineering Program

University of California at Irvine

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

16 Scopus citations

Abstract

Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.

Original language	English
Title of host publication	Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings
Pages	247-260
Number of pages	14
DOIs	https://doi.org/10.1007/978-3-540-78153-0_19
State	Published - 2008
Event	21st International Conference on Architecture of Computing Systems, ARCS 2008 - Dresden, Germany Duration: 25 Feb 2008 → 28 Feb 2008

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4934 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	21st International Conference on Architecture of Computing Systems, ARCS 2008
Country/Territory	Germany
City	Dresden
Period	25/02/08 → 28/02/08

Keywords

Interconnection network
Multiprocessor System-on-Chip (MPSoC)
Network interface
Network-on-Chip (NoC)
Networked Processor Array (NePA)

Access to Document

10.1007/978-3-540-78153-0_19

Cite this

Lee, S. E., Bahn, J. H., Yang, Y. S., & Bagherzadeh, N. (2008). A generic network interface architecture for a Networked Processor Array (NePA). In Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings (pp. 247-260). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4934 LNCS). https://doi.org/10.1007/978-3-540-78153-0_19

Lee, Seung Eun ; Bahn, Jun Ho ; Yang, Yoon Seok et al. / A generic network interface architecture for a Networked Processor Array (NePA). Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings. 2008. pp. 247-260 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{50ba2d881bce43578fa1fee5d0c1d935,

title = "A generic network interface architecture for a Networked Processor Array (NePA)",

abstract = "Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.",

keywords = "Interconnection network, Multiprocessor System-on-Chip (MPSoC), Network interface, Network-on-Chip (NoC), Networked Processor Array (NePA)",

author = "Lee, \{Seung Eun\} and Bahn, \{Jun Ho\} and Yang, \{Yoon Seok\} and Nader Bagherzadeh",

year = "2008",

doi = "10.1007/978-3-540-78153-0\_19",

language = "English",

isbn = "3540781528",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "247--260",

booktitle = "Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings",

note = "21st International Conference on Architecture of Computing Systems, ARCS 2008 ; Conference date: 25-02-2008 Through 28-02-2008",

}

Lee, SE, Bahn, JH, Yang, YS & Bagherzadeh, N 2008, A generic network interface architecture for a Networked Processor Array (NePA). in Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4934 LNCS, pp. 247-260, 21st International Conference on Architecture of Computing Systems, ARCS 2008, Dresden, Germany, 25/02/08. https://doi.org/10.1007/978-3-540-78153-0_19

A generic network interface architecture for a Networked Processor Array (NePA). / Lee, Seung Eun; Bahn, Jun Ho; Yang, Yoon Seok et al.
Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings. 2008. p. 247-260 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4934 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A generic network interface architecture for a Networked Processor Array (NePA)

AU - Lee, Seung Eun

AU - Bahn, Jun Ho

AU - Yang, Yoon Seok

AU - Bagherzadeh, Nader

PY - 2008

Y1 - 2008

N2 - Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.

AB - Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.

KW - Interconnection network

KW - Multiprocessor System-on-Chip (MPSoC)

KW - Network interface

KW - Network-on-Chip (NoC)

KW - Networked Processor Array (NePA)

UR - http://www.scopus.com/inward/record.url?scp=49949110568&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-78153-0_19

DO - 10.1007/978-3-540-78153-0_19

M3 - Conference contribution

AN - SCOPUS:49949110568

SN - 3540781528

SN - 9783540781523

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 247

EP - 260

BT - Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings

T2 - 21st International Conference on Architecture of Computing Systems, ARCS 2008

Y2 - 25 February 2008 through 28 February 2008

ER -

Lee SE, Bahn JH, Yang YS, Bagherzadeh N. A generic network interface architecture for a Networked Processor Array (NePA). In Architecture of Computing Systems - ARCS 2008 - 21st International Conference, Proceedings. 2008. p. 247-260. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-78153-0_19

A generic network interface architecture for a Networked Processor Array (NePA)

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this