TY - GEN
T1 - A graphics and vision unified processor with 0.89μw/fps pose estimation engine for augmented reality
AU - Yoon, Jae Sung
AU - Kim, Jeong Hyun
AU - Kim, Hyo Eun
AU - Lee, Won Young
AU - Kim, Seok Hoon
AU - Chung, Kyusik
AU - Park, Jun Seok
AU - Kim, Lee Sup
PY - 2010
Y1 - 2010
N2 - In many ways, 3D graphics and vision processing are inverse operations. Graphics processing generates pixels from descriptors, while vision generates descriptors from pixels [1]. Since augmented reality (AR) requires both graphics and vision abilities (Fig. 18.6.1), we report a unified processor for graphics, vision, and pose estimation for marker tracking. To process both graphics and vision simultaneously, we use 4 key features: (1) 6-way VLIW datapath design of processing elements, (2) reconfigurable processing elements for graphics and vision modes, (3) a pixel arranger for vision processing that has the inverse characteristic of a graphics rasterizer, and (4) a dedicated pose-estimation engine to generate graphics control data from vision processing. Using these methods, we achieve 371.9GOPS/W for full operation in a VGA image and 0.89μW/fps for pose estimation.
AB - In many ways, 3D graphics and vision processing are inverse operations. Graphics processing generates pixels from descriptors, while vision generates descriptors from pixels [1]. Since augmented reality (AR) requires both graphics and vision abilities (Fig. 18.6.1), we report a unified processor for graphics, vision, and pose estimation for marker tracking. To process both graphics and vision simultaneously, we use 4 key features: (1) 6-way VLIW datapath design of processing elements, (2) reconfigurable processing elements for graphics and vision modes, (3) a pixel arranger for vision processing that has the inverse characteristic of a graphics rasterizer, and (4) a dedicated pose-estimation engine to generate graphics control data from vision processing. Using these methods, we achieve 371.9GOPS/W for full operation in a VGA image and 0.89μW/fps for pose estimation.
UR - https://www.scopus.com/pages/publications/77952197476
U2 - 10.1109/ISSCC.2010.5433907
DO - 10.1109/ISSCC.2010.5433907
M3 - Conference contribution
AN - SCOPUS:77952197476
SN - 9781424460342
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 336
EP - 337
BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
T2 - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
Y2 - 7 February 2010 through 11 February 2010
ER -