Abstract
This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm2. It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is -27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz.
| Original language | English |
|---|---|
| Article number | 9337874 |
| Pages (from-to) | 2438-2442 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 68 |
| Issue number | 7 |
| DOIs | |
| State | Published - Jul 2021 |
Keywords
- Common gate (CG) cross-summing
- input-1dB gain compression (IP1dB)
- phase compensation
- phased-array
- variable gain-low noise amplifier (VGLNA)
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