A low EMI transmitter for DRAM interface with quadrature clock corrector

Dong Wan Ko, Won Young Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents a transmitter with quadrature clock corrector (QCC) and phase controller for reducing EMI problem. The phase controller consists of phase interpolator and transmission gate (TG). The transmission gate is added to turn function on and off. The quadrature clock corrector is used for signal integrity. The circuit is designed in 180-nm CMOS process using 1.8-V supply. The operating frequency is 3.2 Gbps. For duty cycle distortion of 30% ~ 70% and phase error of ±30 degrees, the maximum duty cycle error of corrected clock is about 0.4%, and the phase error between the OUT0 and OUT90 signal is up to about 3.9 degrees. The duty correction time is about 5ns and phase correction time is about 36ns. And the maximum current peak of output drivers is 23% less than that of conventional transmitter.

Original languageEnglish
Title of host publication2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728192017
DOIs
StatePublished - 2021
Event53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of
Duration: 22 May 202128 May 2021

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2021-May
ISSN (Print)0271-4310

Conference

Conference53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/TerritoryKorea, Republic of
CityDaegu
Period22/05/2128/05/21

Keywords

  • DDR
  • EMI
  • Quadrature clock corrector (QCC)
  • Transmitter (TX)

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