A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

Hyung Seok Kim; Hyouk Kyu Cha

doi:10.1142/S0218126618500688

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

Hyung Seok Kim, Hyouk Kyu Cha

Dept. of Electrical and Information Engineering

Seoul National University of Science and Technology (SNUST)

Research output: Contribution to journal › Review article › peer-review

17 Scopus citations

Abstract

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-μm CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79μVrms and noise efficiency factor of 3.16. The IC consumes 2.4μW at 1.2V supply and the die area is 0.09mm².

Original language	English
Article number	1850068
Journal	Journal of Circuits, Systems and Computers
Volume	27
Issue number	5
DOIs	https://doi.org/10.1142/S0218126618500688
State	Published - 1 May 2018

Keywords

current buffer compensation
Neural amplifier
neural recorder
source degeneration
two-stage operational transconductance amplifier

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10.1142/S0218126618500688

Cite this

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title = "A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications",

abstract = "This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-μm CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79μVrms and noise efficiency factor of 3.16. The IC consumes 2.4μW at 1.2V supply and the die area is 0.09mm2.",

keywords = "current buffer compensation, Neural amplifier, neural recorder, source degeneration, two-stage operational transconductance amplifier",

author = "Kim, \{Hyung Seok\} and Cha, \{Hyouk Kyu\}",

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language = "English",

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TY - JOUR

T1 - A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

AU - Kim, Hyung Seok

AU - Cha, Hyouk Kyu

PY - 2018/5/1

Y1 - 2018/5/1

N2 - This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-μm CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79μVrms and noise efficiency factor of 3.16. The IC consumes 2.4μW at 1.2V supply and the die area is 0.09mm2.

AB - This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-μm CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79μVrms and noise efficiency factor of 3.16. The IC consumes 2.4μW at 1.2V supply and the die area is 0.09mm2.

KW - current buffer compensation

KW - Neural amplifier

KW - neural recorder

KW - source degeneration

KW - two-stage operational transconductance amplifier

UR - https://www.scopus.com/pages/publications/85027840196

U2 - 10.1142/S0218126618500688

DO - 10.1142/S0218126618500688

M3 - Review article

AN - SCOPUS:85027840196

SN - 0218-1266

VL - 27

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

IS - 5

M1 - 1850068

ER -

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

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Keywords

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