A Low-Power CMOS Image Sensor with Multiple-Column-Parallel Readout Structure

This paper presents a low-power multiple-column-parallel (MCP) readout CMOS image sensor (CIS) in terms of its structural features. Because each column in an MCP unit performs analog-to-digital (A/D) conversion sequentially, the columns have their own operating periods before and after A/D conversion. Upon completion of A/D conversion in each column, a local bias control (LBC) scheme is applied using a bias circuit of a pixel source follower (SF) to minimize power consumption. In this study, the effectiveness of the proposed LBC scheme is verified for the MCP readout structure. Through simple modification of a column-biasing circuit, the prototype MCP readout CIS achieved significant power savings, which shows its applicability to low-power CIS applications. The prototype CIS was implemented using a 1P6M 0.18- \mu \text{m} CMOS process. A maximum frame rate of 430 fps was achieved while consuming 2.38 mW of power. Compared to a conventional column driver, the proposed LBC scheme reduces the total power consumption by 29.4%, which is an overall power savings of 15%. The prototype CIS also demonstrated figures of merit of 119.1 \mu \text{V}\cdot nJ and 8 \mu \text{V}{\mathrm{ rms}} /kHz.