A low-power, low-noise neural recording amplifier for implantable biomedical devices

Hyung Seok Kim; Hyouk Kyu Cha

doi:10.1109/ISOCC.2016.7799784

A low-power, low-noise neural recording amplifier for implantable biomedical devices

Hyung Seok Kim, Hyouk Kyu Cha

Dept. of Electrical and Information Engineering

Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a low power and low noise neural amplifier IC for processing both action potential and local field potential signals in neural implant devices. Based on a capacitivefeedback topology, the core operational transconductance amplifier utilizes a two-stage structure with current buffer achieving wide bandwidth, large output swing, and small area. The proposed neural amplifier is designed using 0.18μm CMOS process and achieves 46 dB gain, a bandwidth of 0.9 Hz-13.8 kHz, and integrated input-referred noise of 5 μVrms in the range of 1 Hz to 10 kHz. The noise efficiency factor of the designed neural amplifier is 2.6 and consumes 2 μA of current from a 1.2 V supply with an area of 0.136 mm².

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	275-276
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799784
State	Published - 27 Dec 2016
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 23 Oct 2016 → 26 Oct 2016

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Conference

Conference	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	23/10/16 → 26/10/16

Keywords

Capacitive feedback
Neural amplifier
Neural recorder
Operational transconductance amplifier

Access to Document

10.1109/ISOCC.2016.7799784

Cite this

Kim, H. S., & Cha, H. K. (2016). A low-power, low-noise neural recording amplifier for implantable biomedical devices. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 275-276). Article 7799784 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799784

@inproceedings{5fb5d905f9ef4ded8256abe6087421a2,

title = "A low-power, low-noise neural recording amplifier for implantable biomedical devices",

abstract = "This paper presents a low power and low noise neural amplifier IC for processing both action potential and local field potential signals in neural implant devices. Based on a capacitivefeedback topology, the core operational transconductance amplifier utilizes a two-stage structure with current buffer achieving wide bandwidth, large output swing, and small area. The proposed neural amplifier is designed using 0.18μm CMOS process and achieves 46 dB gain, a bandwidth of 0.9 Hz-13.8 kHz, and integrated input-referred noise of 5 μVrms in the range of 1 Hz to 10 kHz. The noise efficiency factor of the designed neural amplifier is 2.6 and consumes 2 μA of current from a 1.2 V supply with an area of 0.136 mm2.",

keywords = "Capacitive feedback, Neural amplifier, Neural recorder, Operational transconductance amplifier",

author = "Kim, \{Hyung Seok\} and Cha, \{Hyouk Kyu\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

year = "2016",

month = dec,

day = "27",

doi = "10.1109/ISOCC.2016.7799784",

language = "English",

series = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "275--276",

booktitle = "ISOCC 2016 - International SoC Design Conference",

}

Kim, HS & Cha, HK 2016, A low-power, low-noise neural recording amplifier for implantable biomedical devices. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799784, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 275-276, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 23/10/16. https://doi.org/10.1109/ISOCC.2016.7799784

A low-power, low-noise neural recording amplifier for implantable biomedical devices. / Kim, Hyung Seok; Cha, Hyouk Kyu.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 275-276 7799784 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low-power, low-noise neural recording amplifier for implantable biomedical devices

AU - Kim, Hyung Seok

AU - Cha, Hyouk Kyu

PY - 2016/12/27

Y1 - 2016/12/27

N2 - This paper presents a low power and low noise neural amplifier IC for processing both action potential and local field potential signals in neural implant devices. Based on a capacitivefeedback topology, the core operational transconductance amplifier utilizes a two-stage structure with current buffer achieving wide bandwidth, large output swing, and small area. The proposed neural amplifier is designed using 0.18μm CMOS process and achieves 46 dB gain, a bandwidth of 0.9 Hz-13.8 kHz, and integrated input-referred noise of 5 μVrms in the range of 1 Hz to 10 kHz. The noise efficiency factor of the designed neural amplifier is 2.6 and consumes 2 μA of current from a 1.2 V supply with an area of 0.136 mm2.

AB - This paper presents a low power and low noise neural amplifier IC for processing both action potential and local field potential signals in neural implant devices. Based on a capacitivefeedback topology, the core operational transconductance amplifier utilizes a two-stage structure with current buffer achieving wide bandwidth, large output swing, and small area. The proposed neural amplifier is designed using 0.18μm CMOS process and achieves 46 dB gain, a bandwidth of 0.9 Hz-13.8 kHz, and integrated input-referred noise of 5 μVrms in the range of 1 Hz to 10 kHz. The noise efficiency factor of the designed neural amplifier is 2.6 and consumes 2 μA of current from a 1.2 V supply with an area of 0.136 mm2.

KW - Capacitive feedback

KW - Neural amplifier

KW - Neural recorder

KW - Operational transconductance amplifier

UR - http://www.scopus.com/inward/record.url?scp=85010379667&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2016.7799784

DO - 10.1109/ISOCC.2016.7799784

M3 - Conference contribution

AN - SCOPUS:85010379667

T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

SP - 275

EP - 276

BT - ISOCC 2016 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th International SoC Design Conference, ISOCC 2016

Y2 - 23 October 2016 through 26 October 2016

ER -

Kim HS, Cha HK. A low-power, low-noise neural recording amplifier for implantable biomedical devices. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 275-276. 7799784. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). doi: 10.1109/ISOCC.2016.7799784

A low-power, low-noise neural recording amplifier for implantable biomedical devices

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this