A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts

Donghoon Choi; Hyouk Kyu Cha

doi:10.1109/ISOCC53507.2021.9613987

A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts

Donghoon Choi, Hyouk Kyu Cha

Dept. of Electrical and Information Engineering

Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

One of the critical issues in bidirectional neural interface systems is that both differential and common-mode interference generated by the stimulator may saturate the neural recording circuit. This paper presents a low-noise neural signal acquisition amplifier that is tolerant to 60 mVpp and 300 mVpp differential and common-mode interference, respectively, while preserving the desired neural signals. The proposed amplifier achieves a closed-loop gain of 20 dB, integrated input referred noise of 2.58 μVrms, and noise efficiency factor of 1.38 while consuming 1.16 μA of current from a 1-V supply. The circuit is designed in 0.18-μm CMOS process and occupies 0.12 mm2 of die area.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	325-326
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613987
State	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 6 Oct 2021 → 9 Oct 2021

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	6/10/21 → 9/10/21

Keywords

common-mode interference
neural amplifier

Access to Document

10.1109/ISOCC53507.2021.9613987

Cite this

Choi, D., & Cha, H. K. (2021). A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 325-326). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613987

@inproceedings{650a10cd05764a57b812d382e31bd8ec,

title = "A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts",

abstract = "One of the critical issues in bidirectional neural interface systems is that both differential and common-mode interference generated by the stimulator may saturate the neural recording circuit. This paper presents a low-noise neural signal acquisition amplifier that is tolerant to 60 mVpp and 300 mVpp differential and common-mode interference, respectively, while preserving the desired neural signals. The proposed amplifier achieves a closed-loop gain of 20 dB, integrated input referred noise of 2.58 μVrms, and noise efficiency factor of 1.38 while consuming 1.16 μA of current from a 1-V supply. The circuit is designed in 0.18-μm CMOS process and occupies 0.12 mm2 of die area.",

keywords = "common-mode interference, neural amplifier",

author = "Donghoon Choi and Cha, \{Hyouk Kyu\}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613987",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "325--326",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

}

Choi, D & Cha, HK 2021, A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 325-326, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 6/10/21. https://doi.org/10.1109/ISOCC53507.2021.9613987

A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts. / Choi, Donghoon; Cha, Hyouk Kyu.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 325-326 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts

AU - Choi, Donghoon

AU - Cha, Hyouk Kyu

PY - 2021

Y1 - 2021

N2 - One of the critical issues in bidirectional neural interface systems is that both differential and common-mode interference generated by the stimulator may saturate the neural recording circuit. This paper presents a low-noise neural signal acquisition amplifier that is tolerant to 60 mVpp and 300 mVpp differential and common-mode interference, respectively, while preserving the desired neural signals. The proposed amplifier achieves a closed-loop gain of 20 dB, integrated input referred noise of 2.58 μVrms, and noise efficiency factor of 1.38 while consuming 1.16 μA of current from a 1-V supply. The circuit is designed in 0.18-μm CMOS process and occupies 0.12 mm2 of die area.

AB - One of the critical issues in bidirectional neural interface systems is that both differential and common-mode interference generated by the stimulator may saturate the neural recording circuit. This paper presents a low-noise neural signal acquisition amplifier that is tolerant to 60 mVpp and 300 mVpp differential and common-mode interference, respectively, while preserving the desired neural signals. The proposed amplifier achieves a closed-loop gain of 20 dB, integrated input referred noise of 2.58 μVrms, and noise efficiency factor of 1.38 while consuming 1.16 μA of current from a 1-V supply. The circuit is designed in 0.18-μm CMOS process and occupies 0.12 mm2 of die area.

KW - common-mode interference

KW - neural amplifier

UR - http://www.scopus.com/inward/record.url?scp=85123385490&partnerID=8YFLogxK

U2 - 10.1109/ISOCC53507.2021.9613987

DO - 10.1109/ISOCC53507.2021.9613987

M3 - Conference contribution

AN - SCOPUS:85123385490

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 325

EP - 326

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

Choi D, Cha HK. A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts. In Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 325-326. (Proceedings - International SoC Design Conference 2021, ISOCC 2021). doi: 10.1109/ISOCC53507.2021.9613987

A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts

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