A New 3-Dimensional Graphene Vertical Transistor with Channel Length Determination Using Dielectric Thickness

This study introduces a novel three-dimensional (3D) vertical field-effect transistor (FET) structure that utilizes two-dimensional (2D) graphene as the channel, with channel length controlled by deposited dielectric thickness. The dielectric deposition process allows for the easier implementation of small-scale features on the order of nanometers compared to traditional patterning processes. Incorporating 3D vertical structures with 2D channel materials enhances device performance beyond conventional planar designs. The fabrication process involves direct graphene growth for the channel and nanometer-scale dielectric deposition for the facile adjustment of channel length. The experimental results validate successful graphene formation and transistor operation, as evidenced by current–voltage characteristics. The 3D Vertical FET holds promise for improved device integration and overall system performance due to its unique device structure and an effective short-channel implementation method. This research underscores the potential of 2D materials in advancing transistor technology, and presents a practical approach for increasing device density and enhancing performance in semiconductor production processes.