A novel 3T DRAM cell with depletion mode PMOS for extended retention time in processing-in-memory applications

Two-transistor dynamic random access memory (2T DRAM) cells for processing-in-memory (PIM) architectures suffer from limitations such as short retention time due to the leakage current, which necessitates frequent refresh operations and leads to high power consumption. In this work, we propose a three-transistor dynamic random access memory (3T DRAM) cell structure that incorporates a series-connected depletion mode PMOS in the read path to overcome these challenges. The key operating principle of the proposed cell structure, the conductance compensation mechanism, effectively suppresses read current variations arising from the storage node voltage drop, thereby enhancing data stability. Through TCAD simulations, we systematically analyzed the electrical characteristics of the proposed 3T DRAM and identified an operating regime where the electrical stability of the device is maximized due to the conductance compensation effect. Furthermore, system-level verification using a customized framework demonstrated that the refresh window of the 3T DRAM cell can be improved by 7.08 times compared to the conventional 2T DRAM. These results prove that the proposed 3T DRAM cell structure can be a promising solution for improving the overall energy efficiency of PIM architectures by effectively reducing the refresh period.