TY - GEN
T1 - A Power-Efficient Low-Noise Neural Recording Amplifier IC with High Tolerance to Stimulation Artifacts
AU - Hong, Soonseong
AU - Cha, Hyouk Kyu
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents a low-power, low-noise neural recording amplifier which is able to cancel up to 1-Vpp common-mode artifacts through a feedback-based common-mode cancellation loop (CMCL). In addition, the proposed neural amplifier achieves a closed-loop gain of 40 dB, integrated input referred noise of 3.26 μVrms over 10 kHz bandwidth, and a noise efficiency factor (NEF) of 1.72. The amplifier is designed using 180 nm CMOS process and consumes 1.9 μW power at 1-V supply.
AB - This paper presents a low-power, low-noise neural recording amplifier which is able to cancel up to 1-Vpp common-mode artifacts through a feedback-based common-mode cancellation loop (CMCL). In addition, the proposed neural amplifier achieves a closed-loop gain of 40 dB, integrated input referred noise of 3.26 μVrms over 10 kHz bandwidth, and a noise efficiency factor (NEF) of 1.72. The amplifier is designed using 180 nm CMOS process and consumes 1.9 μW power at 1-V supply.
KW - common-mode cancellation loop
KW - neural recording amplifier
KW - stimulation artifact
UR - http://www.scopus.com/inward/record.url?scp=85148473660&partnerID=8YFLogxK
U2 - 10.1109/ISOCC56007.2022.10031576
DO - 10.1109/ISOCC56007.2022.10031576
M3 - Conference contribution
AN - SCOPUS:85148473660
T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022
SP - 306
EP - 307
BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th International System-on-Chip Design Conference, ISOCC 2022
Y2 - 19 October 2022 through 22 October 2022
ER -