A Practical Layout Solution for Suppressing MIM Capacitor Coupling Noise in Column-Parallel CIS Design

This paper presents a practical layout strategy to suppress coupling noise in column-parallel CMOS image sensors (CISs), focusing on parasitic coupling between closely integrated Metal-Insulator-Metal (MIM) capacitors. Conventional column parallel layouts suffer from significant coupling noise, primarily due to insufficient shielding of CTM layers, which leads to image artifacts and degraded noise performance. To address this, we propose a partial 4-column shared layout pattern that increases the separation between adjacent MIM capacitors and integrates dedicated ground shielding. The proposed layout was implemented in a fabricated 640 × 480 CIS chip using a 0.18 μm CMOS process with a 5 μm pixel pitch. Post-simulation and experimental results confirm that the proposed design effectively eliminates coupling noise without compromising area efficiency, achieving a temporal noise performance of 121.8 μV_rms even under conditions most susceptible to coupling noise. This demonstrates the practicality and robustness of the practical layout strategy for high-density CIS applications requiring stringent noise performance.